Si4421
CONTROL INTERFACE
Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16- bit command). Bits having no influence (don’t care) are indicated with X. Special care must be taken when the microcontroller’s built- in hardware serial port is used. If the port cannot be switched to
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
∙The TX register is ready to receive the next byte (RGIT)
∙The RX FIFO has received the preprogrammed amount of bits (FFIT)
∙
∙RX FIFO overflow (FFOV) / TX register underrun (RGUR)
∙
∙Negative pulse on the interrupt input pin nINT (EXT)
∙Supply voltage below the preprogrammed value is detected (LBD)
FFIT and FFOV are applicable when the RX FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify the source of the IT, the status bits should be read out.
Timing Specification
Symbol | Parameter | Minimum value [ns] |
tCH | Clock high time | 25 |
tCL | Clock low time | 25 |
tSS | Select setup time (nSEL falling edge to SCK rising edge) | 10 |
tSH | Select hold time (SCK falling edge to nSEL rising edge) | 10 |
tSHI | Select high time | 25 |
tDS | Data setup time (SDI transition to SCK rising edge) | 5 |
tDH | Data hold time (SCK rising edge to SDI transition) | 5 |
tOD | Data delay time | 10 |
Timing Diagram
t |
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| tSHI |
SS |
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nSEL |
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| tCH | tCL |
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| tOD |
| tSH |
SCK |
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tDS | tDH |
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SDI | BIT15 | BIT14 | BIT13 | BIT8 | BIT7 | BIT1 | BIT0 |
SDO | FFIT | FFOV |
| CRL | ATS | OFFS(0) | FIFOOUT |
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