Silicon Laboratories SI4421 Si4421 RX FIFO BUFFERED DATA READ, Recommended Packet Structures

Si4421

RX FIFO BUFFERED DATA READ

In this operating mode, incoming data are clocked into a 16-bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with noise and overloading the external microcontroller.

Interrupt Controlled Mode:

The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case.

Polling Mode:

When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be clocked out by the SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be taken.

An SPI read command is also available to read out the content of the FIFO (Receiver FIFO Read Command, page 21).

FIFO Read Example with FFIT Polling

nSEL
	0		1		2		3		4
SCK
nFFS
						FIFO read out
SDO
		FIFO OUT		FO+1		FO+2		FO+3		FO+4

FFIT

Note: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the duty-cycle of the clock signal is not 50% the shorter period of the clock pulse should be at least 2/fref .

RECOMMENDED PACKET STRUCTURES

	Preamble	Synchron word		Payload	CRC
		(Can be network ID)
Minimum length	4 - 8 bits (1010b or 0101b)	D4h (programmable)	?		4 bit - 1 byte
Recommended length	8 -12 bits (e.g. AAh or 55h)	2DD4h (D4 is programmable)	?		2 byte

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