
Si4421
RX FIFO BUFFERED DATA READ
In this operating mode, incoming data are clocked into a
Interrupt Controlled Mode:
The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the changed FIFO status in this case.
Polling Mode:
When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be clocked out by the SCK. Set the FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need to be taken.
An SPI read command is also available to read out the content of the FIFO (Receiver FIFO Read Command, page 21).
FIFO Read Example with FFIT Polling
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| 0 | 1 | 2 | 3 | 4 |
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SCK |
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nFFS |
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| FIFO read out |
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SDO |
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| FIFO OUT |
| FO+1 |
| FO+2 |
| FO+3 |
| FO+4 |
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FFIT
Note: During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency. When the
RECOMMENDED PACKET STRUCTURES
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| Preamble |
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| Synchron word |
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| Payload |
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| CRC |
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Minimum length |
| 4 - 8 bits (1010b or 0101b) |
| D4h (programmable) | ? |
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| 4 bit - 1 byte | ||||
Recommended length |
| 8 |
| 2DD4h (D4 is programmable) | ? |
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| 2 byte |
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