Si4421, SW Reset Command | Silicon Laboratories SI4421 manual

Sensitive Reset Enabled, Ripple on Vdd :

Si4421

Sensitive Reset Enabled, Ripple on Vdd :

	Vdd	Reset threshold voltage
		(600mV)
		Reset ramp line
		(100mV/ms)
	1.6V
		time
nRes	H
nRes
output	L

Sensitive reset disabled:

	Vdd
	Reset threshold voltage
	(600mV)
	Reset ramp line
	(100mV/ms)
250mV
	time
nRes	H
nRes
output	L

Software reset

Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The result of the command is the same as if power-on reset was occurred but the length of the reset event is much less, 0.25ms typical. The software reset works only when the sensitive reset mode is selected.

Vdd line filtering

During the reset event (caused by power-on, fast positive spike on the supply line or software reset command), it is very important to keep the Vdd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part getting out from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the disturbing signal below 100mVp-pin the DC – 50kHz range for 200ms from Vdd ramp start.. Typical example when a switch-mode regulator is used to supply the radio, switching noise may be present on the Vdd line. Follow the manufacturer’s recommendations how to decrease the ripple of the regulator IC and/or how to shift the switching frequency.

Related control commands

FIFO and Reset Mode Command (page 20)

Setting bit<0> to high will change the reset mode to normal from the default sensitive.

SW Reset Command

Issuing FE00h command will trigger software reset (sensitive reset mode must be enabled). See the Wake-up Timer Command (page 25).

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Image 35

Silicon Laboratories SI4421 manual Si4421, Sensitive Reset Enabled, Ripple on Vdd, FIFO and Reset Mode Command page

Contents

TYPICAL APPLICATIONS FUNCTIONAL BLOCK DIAGRAMFEATURES DESCRIPTION Si4421 DETAILED FEATURE-LEVELDESCRIPTIONRF Power Amplifier PA Data Filtering and Clock Recovery Crystal Oscillator Low Battery Voltage DetectorWake-UpTimer Data Validity Blocks Function Si4421 PACKAGE PIN DEFINITIONSName Type Internal connection Si4421Internal Pin Connections Name Si4421 PIN6 Logic Diagram FSK / DATA / nFFSPIN10 Logic Diagram nRES I/O Note These pins can be left floating Pin Function vs. Operation Mode Si4421Typical Application Recommended supply decoupling capacitor values Recommended Operating Range Si4421 GENERAL DEVICE SPECIFICATIONSAbsolute Maximum Ratings non-operating Si4421 ELECTRICAL SPECIFICATIONDC Characteristics Si4421 AC Characteristics PLL parametersAC Characteristics Receiver AC Characteristics Others Si4421AC Characteristics Transmitter AC Characteristics Turn-on/Turnaroundtimings Note 10 By design Si4421 Timing Diagram Si4421 CONTROL INTERFACETiming Specification Si4421 Control CommandsControl Register Default Values Si4421 Description of the Control CommandsConfiguration Setting Command 2. Power Management Command Si4421 Logic connections between power control bits Si4421 Frequency Setting Command4. Data Rate Command 5. Receiver Control Command Si4421 VDI Logic Diagram Si4421 6. Data Filter Command Si4421 7.FIFO and Reset Mode Command Si4421 8. Synchron Pattern Command9. Receiver FIFO Read Command 10. AFC Command Bit 5-4rl1 to rl0 Si4421 Si4421 11. TX Configuration Control CommandFrequency Setting Command Si4421 13. Transmitter Register Write Command12. PLL Setting Command Si4421 14. Wake-UpTimer Command15.Low Duty-CycleCommand Si4421 Vlb= 2.25 + V · 0.1 V Clock divider configuration Bit Name 17. Status Read CommandSi4421 Si4421 INTERRUPT HANDLING Si4421 TX REGISTER BUFFERED DATA TRANSMISSION Typical TX register usage Si4421 RECOMMENDED PACKET STRUCTURES Si4421 RX FIFO BUFFERED DATA READ Bit Rate 38.4 kbps Si4421 CRYSTAL SELECTION GUIDELINESBit Rate 2.4 kbps Bit Rate 9.6 kbps Si4421 RX-TXALIGNMENT PROCEDURES Si4421 RESET MODES Si4421 Sensitive Reset Enabled, Ripple on VddFIFO and Reset Mode Command page SW Reset Command Channel Selectivity and Blocking Si4421 TYPICAL PERFORMANCE CHARACTERISTICS BER Curves in 868 MHz Band Si4421BER Curves in 433 MHz Band 434 MHz Si4421 Frequency Dependent Component Values Si4421 REFERENCE DESIGNSSchematics Evaluation Board with 50 Ohm Matching Network PCB Layout Top View Bottom View Si4421 Frequency Dependent Component Values SchematicsSi4421 Evaluation Board with Resonant PCB Antenna BIFA Top View Bottom View Si4421PCB Layout Antenna designed for 868/915 MHz band See Detail “A” Section B-B Si4421 PACKAGE INFORMATION16-pinTSSOP Related Resources RELATED PRODUCTS AND DOCUMENTSSi4421 Universal ISM Band FSK Transceiver Demo Boards and Development Kits Si4421