SMSC LAN1198 manual

SMSC AN 12.12 APPLICATION NOTE Revision 1.0 (12-14-09)

AN 12.12LAN9118 Family Programmer Reference Guide

1 Introduction

This application note describes how to successfully develop a network device driver for LAN9118

Family products. It covers device features, software design techniques, network operating system

interfaces, and critical design points. It provides basic design guidelines for incorporating LAN9118

Family products into networked applications. It overviews topics as microprocessor-LAN hardware

interactions; initialization, interrupts, operating system, and communication protocol stack

considerations.It also reviews good design practice for engineers getting acquainted with network

device design.

1.1 References

This manual references the following documents:

SMSC LAN9118 Datasheet

SMSC LAN9117 Datasheet

SMSC LAN9116 Datasheet

SMSC LAN9115 Datasheet

SMSC LAN9118 Reference Design Schematic

SMSC LAN9117 Reference Design Schematic

SMSC LAN9116 Reference Design Schematic

SMSC LAN9115 Reference Design Schematic

Always refer to these documents for complete and current device information. Circuit examples shown

in this document are for illustration only. Follow the corresponding Reference Design Schematic when

implementing an actual circuit design of a LAN9118 Family device.

Please visit SMSC’s website at http://www.smsc.com for the latest updated documentation.

1.2 Document Conventions

In this document, the terms device, network device, controller, and network controller all refer to a

controller in the LAN9118 Family, which includes the LAN9118, LAN9117, LAN9116 and LAN9115.

Host refers to the system into which the device is designed, including the processor, and

application software, etc.

MAC stands for Media Access Controller; the portion of the device responsible for sending or

receiving blocks of data from the network.

A packet is a complete Ethernet frame not yet sent through the MAC, or a frame after it has been

received by the MAC.

A frame is a complete Ethernet data frame with the 802.3 Layer 2 (MAC) header included.

A bit is a single binary digit that has a value of 1 (high) or 0 (low). A field is a continuous string of

bits of whatever length specified.

Contents

Main AN 12.12 LAN9118 Family Programmer Reference Guide 1 Introduction 1.1 References 1.2 Document Conventions 2 Controller Overview 2.1 Block Diagrams 2.1.1 Internal Block Diagram 2.1.2 System Level Block Diagram 2.2 Common Product Family Features Microprocessor/ Microcontroller LAN9118 Family Member Page 3 Register Description Figure 3.1 LAN9118 Family Device Memory MAP MAC CSR Port SLAVE CSR's RESERVED EEPROM Port 3.1 Directly Addressable Registers 3.2 MAC Control and Status Registers 3.3 PHY Registers 3.4 Restrictions on Read-Follow-Write CSR Accesses 3.5 Restrictions on Read-Follow-Read CSR Accesses 4 Programming Recommendations 4.1 The Necessity of Register Ownership 4.2 The Importance of Planning (strcmp(Fail to Plan) == strcmp (Plan to Fail)) 4.3 Orthogonal Register Set 4.4 Register Functionality in the LAN9118 Family Devices 4.5 An Example of Concurrency 4.6 Software Interrupt Feature (SwInt) 4.7 Ownership Policy in the Simple Driver Page 5 Initialization 5.1 MAC Initialization 5.1.1 Software Reset of the MAC 5.1.2 FIFO Allocation and Flow-Control Configuration 5.1.3 Setting the MAC Address 5.1.3.1 The Unicast Address Register 5.2 Configuring Interrupts 5.2.1 Configuring the IRQ Pin 5.2.2 Setting The Interrupt De-assertion Period 5.2.3 Enabling and Disabling Interrupts 5.3 Stopping and Starting the Transmitter 5.4 Stopping and Starting the Receiver 5.5 Configuring Address Filtering Options 5.5.1 Configuring Multicast Filtering 5.5.2 Promiscuous Mode 5.6 PHY Detection and Initialization Page Page 5.7 Switching Between Internal and External PHYs Page 5.8 Examples of PHY MII Register Reads and Writes Page Page 6 Transmit Packet Processing 6.1 Transmit Data Transfer 6.2 Command Word Construction 6.3 Per Packet Flow Control 6.4 Packet Transfer Completion: Management Statistics 6.5 Transmit Packet Examples Page Revision 1.0 (12-14-09) 32 SMSC AN 12.12 Figure 6.1 Multiple (3) Buffer Data Single Packet Transfer Sequence Table6.6 TX_C MD_A for Segment 1 0x0 0x3 1 0 0x1d Table6.7 TX_C MD_B for Segment 1 PACKET Table6.8 TX_C MD_A for Segment 2 Table6.9 TX_CMD_B for Segment 2 6.6 The Overall Packet Transmit Process Page 7 Receive Packet Processing Page 7.1 Receive Data Transfer 7.2 Purging Receive Packets 7.3 Flow Control Function 7.3.1 Backpressure 7.3.2 Pause Frames 8 Instrumentation and Debug 8.1 Debug Prints 8.1.1 SMSC_TRACE(message, parameters) 8.1.2 SMSC_WARNING(message, parameters) 8.1.3 SMSC_ASSERT(condition) 8.2 GPIO pins in Conjunction with Oscilloscope 8.3 TxCLK and RxCLK 8.4 Error Interrupts are Invaluable Tools 8.5 Integrating the Driver: Early Testing 9 Power Management Events 9.1 System Description