LAN9118 Family Programmer Reference Guide
SMSC AN 12.12 7 Revision 1.0 (12-14-09)
APPLICATION NOTE
3.2 MAC Control and Status Registers
The registers listed below are accessed indirectly through the MAC_CSR_CMD and MAC_CSR_DATA
Registers. These registers are used in Section 5.1.2 and Section 5.5.
.
3.3 PHY Registers
The PHY registers are accessed through two levels of indirection: through MAC_CSR_CMD/DATA
Registers and the MII_ACCESS/DATA Registers. The PHY provides its own interrupt source and mask
register; a “master” enable/disable bit for the PHY interrupts is found in the PHY_INT_EN bit in the
INT_STS/INT_EN registers.
Individual PHY Registers are identified through an index field located in the MII_ACC register . PHY
Register Indices are shown in Table3 .3 below. These registers are used in Section 5.6.
Note: PHY Register bits designated as NASR are reset when the SIM CSR Software Reset is
generated. The NASR designation is only applicable when bit 15 of the PHY Basic Control
Register (Reset) is set.
Table3.2 LAN9118 Family MAC CSR Register Map
MAC CONTROL AND STATUS REGISTERS
INDEX SYMBOL REGISTER NAME DEFAULT
1 MAC_CR MAC Control Register 00040000h
2 ADDRH MAC Address High 0000FFFFh
3 ADDRL MAC Address Low FFFFFFFFh
4 HASHH Multicast Hash Table High 00000000h
5 HASHL Multicast Hash Table Low 00000000h
6 MII_ACC MII Access 00000000h
7 MII_DATA MII Data 00000000h
8 FLOW Flow Control 00000000h
9 VLAN1 VLAN1 Tag 00000000h
10 VLAN2 VLAN2 Tag 00000000h
11 WUFF Wake-up Frame Filter 00000000h
12 WUCSR Wake-up Status and Control 00000000h