LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09) 10 SMSC AN 12.12
APPLICATION NOTE
The fundamental operations of the driver are initialization, transmit packet processing, receive packet
processing, and interrupt processing. In addition, the driver needs to manage link negotiation and
interact with the operating system. The driver may be required to keep statistics, manage power
consumption, and control other functions.
4.1 The Necessity of Register OwnershipWriting a driver is a complex task. Every possible sequence of operations needs to be considered. A
commonly encountered problem is having to share a resource, such as a CSR, between two or more
code threads. Having multiple code threads access the same resource only increases the challenge.
If one thread is interrupted by a second thread, such that both threads are attempting to modify the
resource at the same time, unpredictable behavior may result. Collectively, these conflicts are known
as synchronization issues.
4.2 The Importance of Planning(strcmp(“Fail to Plan”) == strcmp (“Plan to Fail”))To prevent this type of unpredictable behavior, the first step in writing a driver is to plan which portions
of the driver will access which registers. Every potential synchronization issue needs to be considered
before the first line of code is written. Failure to do so will result in errors that are intermittent and
extremely difficult to reproduce. Even worse, these problems may not even surface until well into the
driver development. Initially, the driver may appear to work, but as integration proceeds and more
threads are added, and the environment becomes more complex, the driver may suddenly and
inexplicably develop problems.
4.3 Orthogonal Register SetIn order to prevent these types of synchronization issues, the register set of every LAN9118 Family
device has been organized so that each register only needs to be accessed by a single thread.
Registers which are accessed by the receive process do not need to be accessed by the transmit or
initialization processes, and so on. In addition, registers used to manage flow control and separated
from those used to manage the link.
The design of the register set, which is “orthogonal” allows the multiple threads within the driver to be
interweaved, or run concurrently without interfering with each other.
Table3.5 Special Back-to-Back Cycles
AFTER READING... PERFORM X READS OF BYTE_TEST BEFORE READING...
RX Data FIFO 3 RX_FIFO_INF
RX Status FIFO 3 RX_FIFO_INF
TX Status FIFO 3 TX_FIFO_INF
RX_DROP 4 RX_DROP