SMSC LAN1198 - page 21

LAN9118 Family Programmer Reference Guide

SMSC AN 12.12 21 Revision 1.0 (12-14-09)

APPLICATION NOTE

Figure 5.1 PHY Access Command and Data PathwaysThe driver can verify the existence of the internal PHY by reading the PHY Registers 2 and 3 at PHYAddress 1 and ensuring the contents are 0x0007 and 0xc0c1 respectively. The existence of externalPHYs is determined by reading the same two PHY Registers at PHY Addresses 0x02 through 0x30.If values of 0xffff and 0xffff are obtained, ther e is no PHY at the given PHY Address. The driver can reset the internal PHY by writing the Reset bit (15) in the Basic Control Register(index 0). This bit is self clearing and can be polled (read back) in order to coordinate the PHY resetcompletion with driver execution. After resetting the PHY, the driver should wait at least 50ms beforeattempting any further operations on the PHY.Auto-negotiation begins by enabling all the PHY capabilities in the Auto-Negotiation Advertisement(0x1e1), then setting the Auto-negotiation Enable and Auto-negotiate Restart bits (12 and 9) in the

Host Processo r

Slave CSRs (Directly Addressable)

Host

Bus

Interface

MAC_CSR_CMD Register

MAC_CSR_Data Register

0xA4

0xA8

Offset

MAC CSRs

MII_ACC_Register

MII_Data_Register

0x6

0x7

Index

Internal MII External MII

(LAN9115 and

LAN9117

PH Y CS R s ( I nt er n al P HY)

Basic Control Register

Basic Status Regist er

0

1

PHY Register Index

2

3

4

5

6

17

29

30

31

PHY ID Register 1

PHY ID Register 2

A/N Adv ertisem ent Reg

Link Partner Ability R eg

A/N Expansion Regis ter

Mode Control Register

Interrupt Source Regist er

Interrupt Mask Register

Special Control Regist er

PHY Address = 00001b

PHY CSRs (External PHY)

PHY Address /= 00001b

Contents

Main AN 12.12 LAN9118 Family Programmer Reference Guide 1 Introduction 1.1 References 1.2 Document Conventions 2 Controller Overview 2.1 Block Diagrams 2.1.1 Internal Block Diagram 2.1.2 System Level Block Diagram 2.2 Common Product Family Features Microprocessor/ Microcontroller LAN9118 Family Member Page 3 Register Description Figure 3.1 LAN9118 Family Device Memory MAP MAC CSR Port SLAVE CSR's RESERVED EEPROM Port 3.1 Directly Addressable Registers 3.2 MAC Control and Status Registers 3.3 PHY Registers 3.4 Restrictions on Read-Follow-Write CSR Accesses 3.5 Restrictions on Read-Follow-Read CSR Accesses 4 Programming Recommendations 4.1 The Necessity of Register Ownership 4.2 The Importance of Planning (strcmp(Fail to Plan) == strcmp (Plan to Fail)) 4.3 Orthogonal Register Set 4.4 Register Functionality in the LAN9118 Family Devices 4.5 An Example of Concurrency 4.6 Software Interrupt Feature (SwInt) 4.7 Ownership Policy in the Simple Driver Page 5 Initialization 5.1 MAC Initialization 5.1.1 Software Reset of the MAC 5.1.2 FIFO Allocation and Flow-Control Configuration 5.1.3 Setting the MAC Address 5.1.3.1 The Unicast Address Register 5.2 Configuring Interrupts 5.2.1 Configuring the IRQ Pin 5.2.2 Setting The Interrupt De-assertion Period 5.2.3 Enabling and Disabling Interrupts 5.3 Stopping and Starting the Transmitter 5.4 Stopping and Starting the Receiver 5.5 Configuring Address Filtering Options 5.5.1 Configuring Multicast Filtering 5.5.2 Promiscuous Mode 5.6 PHY Detection and Initialization Page Page 5.7 Switching Between Internal and External PHYs Page 5.8 Examples of PHY MII Register Reads and Writes Page Page 6 Transmit Packet Processing 6.1 Transmit Data Transfer 6.2 Command Word Construction 6.3 Per Packet Flow Control 6.4 Packet Transfer Completion: Management Statistics 6.5 Transmit Packet Examples Page Revision 1.0 (12-14-09) 32 SMSC AN 12.12 Figure 6.1 Multiple (3) Buffer Data Single Packet Transfer Sequence Table6.6 TX_C MD_A for Segment 1 0x0 0x3 1 0 0x1d Table6.7 TX_C MD_B for Segment 1 PACKET Table6.8 TX_C MD_A for Segment 2 Table6.9 TX_CMD_B for Segment 2 6.6 The Overall Packet Transmit Process Page 7 Receive Packet Processing Page 7.1 Receive Data Transfer 7.2 Purging Receive Packets 7.3 Flow Control Function 7.3.1 Backpressure 7.3.2 Pause Frames 8 Instrumentation and Debug 8.1 Debug Prints 8.1.1 SMSC_TRACE(message, parameters) 8.1.2 SMSC_WARNING(message, parameters) 8.1.3 SMSC_ASSERT(condition) 8.2 GPIO pins in Conjunction with Oscilloscope 8.3 TxCLK and RxCLK 8.4 Error Interrupts are Invaluable Tools 8.5 Integrating the Driver: Early Testing 9 Power Management Events 9.1 System Description