LAN9118 Family Programmer Reference Guide
SMSC AN 12.12 17 Revision 1.0 (12-14-09)
APPLICATION NOTE
has the bits corresponding with the interrupts to be enabled set to “1”. To disable specific interrupts,
AND the contents with a bit-mask which has the bits corresponding to the interrupts to be disabled set
to “0”. Write the modified value back to the register.
Per Section 3.4 and Section 3.5, the INT_EN register requires a “settl ing” time before its effects are
felt . Satisfying this timing is critical because this register is shared between send and receive paths.
The status of an interrupt source is reflected in the INT_STS register regardless of whether or not the
source is actually enabled as an IRQ interrupt. This register also handles interrupt acknowledgement.
Writing a “1” to any bit clears it as long as the interrupt source is no longer active. The interrupt bit will
not be cleared if the interrupt condition is still pending regardless of writing 1 to the bit.
The interrupt controller has the ability to generate an IRQ on a Power Management Event when the
controller is in the D0, D1 or D2 power states.
5.3 Stopping and Starting the Transmitter
To halt the transmitter, the host can set the STOP_TX bit in the TX_CFG register. The transmitter will
finish sending the current frame (if there is a frame transmission in progress). When the transmitter
has pushed the TX Status for this frame onto the TX status FIFO, it will clear the TX_CFG:STOP_TX
and TX_CFG:TX_ON bits, and then pulse the INT_STS:TXSTOP_INT bit.
Once the transmitter is stopped, the host can clear the TX Status and TX Data FIFOs by setting the
TX_CFG:TXS_DUMP and TXD_DUMP bits. It can also disable the MAC by clearing MAC_CR:TXEN.
To re-enable the transmitter, the host must set the TX_CFG:TX_ON and MAC_CR:TXEN bits. When
the transmitter is re-enabled, it will begin transmitting any packets that are in the TX DATA FIFO.
5.4 Stopping and Starting the Receiver
To stop the receiver, the host must clear the MAC_CR:RXEN bit in the MAC Control Register. When
the receiver is halted, the INT_STS:RXSTOP_INT bit will be set. Once stopped, the host can optionally
clear the RX Status and RX Data FIFOs. The host can re-enable the receiver by setting the
MAC_CR:RXEN bit.