LAN9118 Family Programmer Reference Guide
Revision 1.0 (12-14-09) 12 SMSC AN 12.12
APPLICATION NOTE
The need of maintaining the independence of the transmit and receive packet processing functions
has already been mentioned. For example, suppose that the transmit thread needs to execute
operations T0-T9 below as part of transmitting a packet:
At the same time the receive thread needs to execute operations R0-R9 as part of receiving a packet:
It is entirely possible for these operations to be interleaved as follows:
The only requirement is that within each thread, proper order of the data stream must be maintained;
Receive operations must remain properly ordered and transmit operations likewise must remain
properly ordered. Aside from the required ordering within each data stream, the streams can be
interweaved arbitrarily; the controller must be capable of handling any legitimate possibility.
Interleaving also applies to the host interface. If both transmit and receive DMA channels are used,
the transmit DMA channel can be writing a packet while the receive DMA channel is concurrently
reading a packet. LAN9118 Family devices have been designed specifically to handle these kinds of
cases.
Interleaved accesses also support interleaving between the link and filter management threads
concurrent with the transmit and receive threads already described. This could occur if the transmit
and receive threads were both involved in DMA activities, while the CPU was handling the filter thread
at the moment a link-state change interrupted the processor. Because of the orthogonality of the
register set, all four threads could be interleaved successfully without errors.
4.6 Software Interrupt Feature (SwInt)LAN9118 Family devices provide a software interrupt feature (Swint). This feature allows the driver to
force the device to activate its IRQ signal. This is done by setting the INT_EN:SW_INT_EN bit. One
use of this feature is to allow the driver to verify that it has properly registered the Interrupt Service
Routine to the correct IRQ during initialization.
Another use of this feature is to protect critical registers. One case where this feature can be used is
when an ISR accesses a register and it is critical that this register not be accessed outside the ISR.
If a code segment outside the ISR needs to access this register, rather than access the register directly,
the segment can set a flag bit indicating that the register should be accessed and then invoke the ISR
via the Swint feature. When the ISR sees the flag bit, it performs the register access on behalf of the
code segment. The thread which called the ISR would also need some mechanism for determining
that the request had completed, such as polling a status bit from the ISR.
Of course, this only works if there is only one segment of code outside the ISR needing to access the
critical register. If there are multiple threads accessing the register, they need additional
synchronization between them. Otherwise the activity of one thread may undo another; and if multiple
threads call the ISR using the same flag bit, the ISR will not be able to tell which thread called it.
TIME 0, T+1, T+2, T+3, … T+19
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
TIME 0, T+1, T+2, T+3, … T+19
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9
TIME 0, T+1, T+2, T+3, … T+19
T0 T1 R0 T2 R1 R2 T3 R3 R4 T4 T5 T6 T7 R5 R6 T8 R7 R8 R9 T9