SMSC LAN1198 - page 25

LAN9118 Family Programmer Reference Guide

SMSC AN 12.12 25 Revision 1.0 (12-14-09)

APPLICATION NOTE

Step Three:

Keep reading the MAC_CSR_CMD Register until the CSR Busy Bit =0.

Load the MII write command word (MII W/nR == 1) that is to be written to the MII ACC register into

the MAC_CSR_Data register. The command word will write the contents of the MII DATA register to

the PHY Advertisement register (0x4) (note that the lighter-shaded heading is expressed in MII ACC

register terms).

Step Four:

Write the command word into the MAC_CSR_CMD register. This causes the MII ACC register (0x06)

to be written (R/nW == 0) with the contents of the MAC_CSR_Data register, which in turn causes the

MII register write to be executed.

Steps 5-8:

5. Read the MAC_CSR_CMD Register until the Busy Bit = 0.

6. Load the MAC_CSR_CMD Register as follows: CSR Busy = 1, R/nW = 1 (Read), CSR Address

= 0x06 (MII_ACC Register)

7. Read the MAC_CSR_CMD Register until the Busy Bit = 0

8. Read the MAC_CSR_DATA Register. Repeat steps 6-8 until the MII Busy Bit (Bit 0) = 0.

Example 2: Read the PHY Status register (register 1)

Step One:

Load the MAC_CSR_Data register with the MII ACC register command word to read (MII W/nR == 1)

PHY register 1 (MII Register == 1). Note that the lighter-shaded heading is expressed in MII ACC

terms.

Step Two:

Write the command word into the MAC_CSR_CMD register. This causes the contents of the

MAC_CSR_Data register to be written (R/nW == 0) to the MII ACC register (0x06), which executes

the PHY read. The resulting read from the PHY is then loaded to the MII Data register

MAC_CSR_DATA (TO BE LOADED INTO MII ACC REGISTER)

Reserved

(31:16)

PHY Address

(15:11)

MII Register

(10:6)

Reserved

(5:2)

MII

W/nR

MII

Busy

0x1 0x4 1 1

MAC_CSR_CMD (ACCESSING MII_ACC REGISTER)

CSR Busy R/nW Reserved (29:8) CSR Address (7:0)

1 0 0x06

MAC_CSR_DATA

Reserved

(31:16)

PHY Address

(15:11)

MII Register

(10:6)

Reserved

(5:2)

MII

W/nR

MII

Busy

0x1 0x1 0 1

Contents

Main AN 12.12 LAN9118 Family Programmer Reference Guide 1 Introduction 1.1 References 1.2 Document Conventions 2 Controller Overview 2.1 Block Diagrams 2.1.1 Internal Block Diagram 2.1.2 System Level Block Diagram 2.2 Common Product Family Features Microprocessor/ Microcontroller LAN9118 Family Member Page 3 Register Description Figure 3.1 LAN9118 Family Device Memory MAP MAC CSR Port SLAVE CSR's RESERVED EEPROM Port 3.1 Directly Addressable Registers 3.2 MAC Control and Status Registers 3.3 PHY Registers 3.4 Restrictions on Read-Follow-Write CSR Accesses 3.5 Restrictions on Read-Follow-Read CSR Accesses 4 Programming Recommendations 4.1 The Necessity of Register Ownership 4.2 The Importance of Planning (strcmp(Fail to Plan) == strcmp (Plan to Fail)) 4.3 Orthogonal Register Set 4.4 Register Functionality in the LAN9118 Family Devices 4.5 An Example of Concurrency 4.6 Software Interrupt Feature (SwInt) 4.7 Ownership Policy in the Simple Driver Page 5 Initialization 5.1 MAC Initialization 5.1.1 Software Reset of the MAC 5.1.2 FIFO Allocation and Flow-Control Configuration 5.1.3 Setting the MAC Address 5.1.3.1 The Unicast Address Register 5.2 Configuring Interrupts 5.2.1 Configuring the IRQ Pin 5.2.2 Setting The Interrupt De-assertion Period 5.2.3 Enabling and Disabling Interrupts 5.3 Stopping and Starting the Transmitter 5.4 Stopping and Starting the Receiver 5.5 Configuring Address Filtering Options 5.5.1 Configuring Multicast Filtering 5.5.2 Promiscuous Mode 5.6 PHY Detection and Initialization Page Page 5.7 Switching Between Internal and External PHYs Page 5.8 Examples of PHY MII Register Reads and Writes Page Page 6 Transmit Packet Processing 6.1 Transmit Data Transfer 6.2 Command Word Construction 6.3 Per Packet Flow Control 6.4 Packet Transfer Completion: Management Statistics 6.5 Transmit Packet Examples Page Revision 1.0 (12-14-09) 32 SMSC AN 12.12 Figure 6.1 Multiple (3) Buffer Data Single Packet Transfer Sequence Table6.6 TX_C MD_A for Segment 1 0x0 0x3 1 0 0x1d Table6.7 TX_C MD_B for Segment 1 PACKET Table6.8 TX_C MD_A for Segment 2 Table6.9 TX_CMD_B for Segment 2 6.6 The Overall Packet Transmit Process Page 7 Receive Packet Processing Page 7.1 Receive Data Transfer 7.2 Purging Receive Packets 7.3 Flow Control Function 7.3.1 Backpressure 7.3.2 Pause Frames 8 Instrumentation and Debug 8.1 Debug Prints 8.1.1 SMSC_TRACE(message, parameters) 8.1.2 SMSC_WARNING(message, parameters) 8.1.3 SMSC_ASSERT(condition) 8.2 GPIO pins in Conjunction with Oscilloscope 8.3 TxCLK and RxCLK 8.4 Error Interrupts are Invaluable Tools 8.5 Integrating the Driver: Early Testing 9 Power Management Events 9.1 System Description