SMSC LAN1198 - page 31

LAN9118 Family Programmer Reference Guide

SMSC AN 12.12 31 Revision 1.0 (12-14-09)

APPLICATION NOTE

Keep in mind that this example is running in a Little Endian environment. To begin the transfer

sequence, write the two command words as DWORDs, followed by the packet data. Since the transfer

is aligned on 4-byte boundaries, the data transfer start address must begin from 0xb4002010 and

continue up to and including 0xb4002060. Table6.5, "Single Buffer Single Packet Data Transfer

Sequence" shows the sequence of data transferred from Tabl e 6.2 : Transmit Packet Example’s

memory into the TX_DATA_FIFO. To read the Table6.5, start from the upper left portion, and fol lowing

the Host Source Address (light grey) headings down, then zigzag back up and down through the

middle, and then the right-hand columns, so that the transfer appears thus:

The second example will demonstrate how to chain transfers together into a single packet. We will

re-use the sample packet shown in Tabl e 6. 2 , and instead of a single transfer, we will make 3 separate

transfers; 29 bytes to start, then 32 bytes, then the remaining 17 bytes. Visually the chained transfer

appears like this:

Table6.4 Transmit Command Words

TX_CMD_B

Packet Tag 15 14 13 12 11 Packet Length

0x1234 0x4e

Table6.5 Single Buffer Single Packet Data Transfer Sequence

HOST

SOURCE

ADDRESS

TX_DATA_FIFO

DATA

TRANSFER 1

HOST

SOURCE

ADDRESS

TX_DATA_FIFO

TRANSFER

CONT.

HOST

SOURCE

ADDRESS

TX_DATA_FIFO

TRANSFER

CONT.

TX_CMD_A 0x0003304e 0xb4002028 0xf0068000 0xb4002048 0x726f6600

TX_CMD_B 0x1234004e 0xb400202c 0x5081aa6a 0xb400204c 0x43534d53

0xb4002010 0x00XXXXXX 0xb4002030 0x5381aa76 0xb4002050 0x44202e4d

0xb4002014 0xdea0830e 0xb4002034 0x01e70496 0xb4002054 0x64697662

0xb4002018 0x0f8000ff 0xb4002038 0x384aa9bd 0xb4002058 0x4c654720

0xb400201c 0x08715571 0xb400203c 0x7cd60a0d 0xb400205c 0x6e616d62

0xb4002020 0x00004500 0xb4002040 0xff10506c 0xb4002060 0xYYYYYY21

0xb4002024 0x40561128 0xb4002044 0x0029f9ff

Contents

Main AN 12.12 LAN9118 Family Programmer Reference Guide 1 Introduction 1.1 References 1.2 Document Conventions 2 Controller Overview 2.1 Block Diagrams 2.1.1 Internal Block Diagram 2.1.2 System Level Block Diagram 2.2 Common Product Family Features Microprocessor/ Microcontroller LAN9118 Family Member Page 3 Register Description Figure 3.1 LAN9118 Family Device Memory MAP MAC CSR Port SLAVE CSR's RESERVED EEPROM Port 3.1 Directly Addressable Registers 3.2 MAC Control and Status Registers 3.3 PHY Registers 3.4 Restrictions on Read-Follow-Write CSR Accesses 3.5 Restrictions on Read-Follow-Read CSR Accesses 4 Programming Recommendations 4.1 The Necessity of Register Ownership 4.2 The Importance of Planning (strcmp(Fail to Plan) == strcmp (Plan to Fail)) 4.3 Orthogonal Register Set 4.4 Register Functionality in the LAN9118 Family Devices 4.5 An Example of Concurrency 4.6 Software Interrupt Feature (SwInt) 4.7 Ownership Policy in the Simple Driver Page 5 Initialization 5.1 MAC Initialization 5.1.1 Software Reset of the MAC 5.1.2 FIFO Allocation and Flow-Control Configuration 5.1.3 Setting the MAC Address 5.1.3.1 The Unicast Address Register 5.2 Configuring Interrupts 5.2.1 Configuring the IRQ Pin 5.2.2 Setting The Interrupt De-assertion Period 5.2.3 Enabling and Disabling Interrupts 5.3 Stopping and Starting the Transmitter 5.4 Stopping and Starting the Receiver 5.5 Configuring Address Filtering Options 5.5.1 Configuring Multicast Filtering 5.5.2 Promiscuous Mode 5.6 PHY Detection and Initialization Page Page 5.7 Switching Between Internal and External PHYs Page 5.8 Examples of PHY MII Register Reads and Writes Page Page 6 Transmit Packet Processing 6.1 Transmit Data Transfer 6.2 Command Word Construction 6.3 Per Packet Flow Control 6.4 Packet Transfer Completion: Management Statistics 6.5 Transmit Packet Examples Page Revision 1.0 (12-14-09) 32 SMSC AN 12.12 Figure 6.1 Multiple (3) Buffer Data Single Packet Transfer Sequence Table6.6 TX_C MD_A for Segment 1 0x0 0x3 1 0 0x1d Table6.7 TX_C MD_B for Segment 1 PACKET Table6.8 TX_C MD_A for Segment 2 Table6.9 TX_CMD_B for Segment 2 6.6 The Overall Packet Transmit Process Page 7 Receive Packet Processing Page 7.1 Receive Data Transfer 7.2 Purging Receive Packets 7.3 Flow Control Function 7.3.1 Backpressure 7.3.2 Pause Frames 8 Instrumentation and Debug 8.1 Debug Prints 8.1.1 SMSC_TRACE(message, parameters) 8.1.2 SMSC_WARNING(message, parameters) 8.1.3 SMSC_ASSERT(condition) 8.2 GPIO pins in Conjunction with Oscilloscope 8.3 TxCLK and RxCLK 8.4 Error Interrupts are Invaluable Tools 8.5 Integrating the Driver: Early Testing 9 Power Management Events 9.1 System Description