SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.7.1The Use of NDATACS

Direct access to the Data Register is controlled via the nDATACS pin. This is can be accomplished whether the LAN91C111 is configured for synchronous or asynchronous operations. Accessing the LAN91C111 via the nDATACS pin bypasses the internal Bus Interface Unit (BIU) decoders and accesses designated by the nDATACS are steered towards the Data Register only. All accesses are 32-bits in nature and used to read or write directly to the internal data register memory of the LAN91C111 device.

In addition to direct access to the Data Register via the nDATACS signal, there is also an additional feature available, Burst Mode operation. Burst mode operations can be accomplished in synchronous mode. By using the nCYCLE pin in conjunction with the nDATACS, the design engineer is capable of direct data register access in a burst style operation. Control of the speed of bursting to the LAN91C111 can be accomplished via the nRDYRTN signal. The nRDYRTN signal is used to insert wait states in a burst type cycle. By combining these signals, multiple speeds of memory can be controlled. We will examine both a burst and non-burst mode (asynchronous) transfers later on in this document.

The proper use of this type of accesses does require that the LAN91C111 be configured correctly. The entire setup of the LAN91C111 is beyond the scope of this document and a design engineer should review the LAN91C111 Data Sheet. One area of significance that will be covered and is common among all caveats of nDATACS operation is the use of the Pointer Register.

3.7.2Pointer Register

The Pointer Register is an internal register where the control of the internal Data Register(s) (FIFO’s) is done. This register defines where the cycle is being presented to the Data Register and also other control information and options.

The Pointer Register also controls the Auto-Increment feature of the FIFO. This will be discussed in detail as well. Control as to whether to information is read or written is done by the READ bit within this register. The RCV bit controls the area written to or read from. If this bit is set, the receive area of the FIFO is accessed, if cleared the transmit area of the FIFO is accessed. The contents and settings of this register will be discussed next.

OFFSET

 

 

NAME

 

TYPE

 

 

SYMBOL

6

 

 

POINTER REGISTER

 

READ/WRITE

 

PTR

 

 

 

 

 

 

 

 

 

 

 

 

 

HIGH

 

RCV

AUTO

 

READ

 

Reserved

NOT

 

 

POINTER HIGH

BYTE

 

INCR.

 

 

EMPTY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

0

0

 

0

0

0

LOW

 

 

 

 

 

 

POINTER LOW

 

 

 

BYTE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

0

 

0

0

 

0

0

0

Figure 3.6 Pointer Register

RCV

The RCV bit being set indicates that the operation is to access the receive area and accesses the RX FIFO as the packet number. When this bit is cleared, the write area of the TX FIFO is being accessed.

AUTOINCR

The AUTOINCR bit indicates whether the internal MMU is to automatically change the address for the next Data Register accesses. Note: If AUTOINCR is not set, the pointer must be loaded with a dword- aligned value prior to the next access of the Data Register.

SMSC AN 9.6

15

Revision 1.0 (08-14-08)

APPLICATION NOTE