SMSC LAN91C111 10.2.9 General Purpose Output, 10.2.10 Reset, 10.2.11 Interrupt Pin (INTR0), 10.2.12 SRAM Interface, 10.2.13X25OUT Clock Output Pin, 10.2.14 Programmable LED’s

SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

10.2.9 General Purpose Output

The General Purpose Control pin (nCNTRL) and the General Purpose Control bit (GPCNTRL) have been added to the LAN91C111. The GPCNTRL bit has been replaced the FULL STEP bit in the LAN91C100FD Configuration Register. It can be used to select the signaling mode for the external PHY or as a general-purpose non-volatile configuration pin. Its inverse value drives the nCNTRL output pin, which is typically connected to a SELECT pin of the external PHY device such as a power enable. The GPCNTRL bit defaults low at power up.

10.2.10 Reset

When the Reset pin is asserted, the LAN91C111 performs an internal system reset. It resets both the MAC and the internal PHY and programs all the registers to their default value. The LAN91C111 will then read the EEPROM device through the EEPROM interface if enabled and the EEPROM is present.

10.2.11 Interrupt Pin (INTR0)

The LAN91C111 has only one interrupt pin (INTR0). The LAN91C100FD INT SEL 0-1 bits in the Configuration Register (bank 1) were changed to RESERVED. In order for software that uses interrupts to work properly with the LAN91C111, both RESERVED bits in the Configuration register must be 0 regardless of the interrupt number (IRQ) used in the host. INTR0 can be connected through hardware jumpers to select different IRQ’s.

10.2.12 SRAM Interface

Since the LAN91C111 SRAM is internal, the following pins for SRAM interface have been removed. RD[0-31], RA[2-16], nROE, nRWE[0-3], RDMAH, RCVDMA. The LAN91C111 has a built-in 8K byte internal SRAM with a page size of 2k. The storage capacity of the chip is 4 packets (total of transmit

+receive). The MMU automatically, and dynamically, allocates the internal 8K internal SRAM is between transmitted and received packets.

10.2.13X25OUT Clock Output Pin

This LAN91C111 output pin is added to allow an external PHY to utilize this clock signal. This eliminates any requirement for an additional crystal oscillator if the customer uses an external PHY (such as an external fiber or Home PNA PHY).

10.2.14 Programmable LED’s

The two LAN91C111 LED outputs can be programmed by setting LS[0-2]A and LS[0-2]B to select any two of the following function: Link, Activity, Transmit, Receive, Duplex, 10/100Mbps. Please the LED selection table of the datasheet for details.

10.2.15 TP Interface

The LAN91C111 integrates the PHY and contains the TP interface for transmitting and receiving. The TP input and output pins (TPO+, TPO-, TPI+, TPI-) can be connected to a transformer (magnetic) for 100BASE-TX or 10BASE-T applications.

10.2.16 RBIAS pin

The LAN91C111 RBIAS pin is used to set transmit current level. An external resistor connected between this pin and ground will set the output current for the TP transmits outputs.

SMSC AN 9.6 59 Revision 1.0 (08-14-08)

APPLICATION NOTE