SMSC LAN91C111
crossing the MII interface (internal to the 91C111). The loopback at point C is referred to as an external loopback, which loops the packet back after leaving the PHY and the external magnetics.
This final type of loopback testing allows the design engineer to complete the circuit to ensure proper operation of their design. While the internal loopback tests provide excellent functional testing, external loopback also tests the components outside the LAN91C111 as well.
ABC
Ethernet Protocol
Handler TX (EPH)
RX
MAC | MII | PHY | MAGNETICS | RJ45 |
| SWFDUP |
| DPLX |
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| BIT IN |
| BIT IN |
| LPBK BIT |
LOOPBACK TYPE | TCR | FDUPLX BIT IN TCR | RPCR* | EHPLOOP BIT IN TCR | IN PHY |
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EPH | X | X | X | 1 | X |
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PHY Half | 0 | 1 | 0 | 0 | 1 |
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PHY Full | 1 | X | 1 | 0 | 1 |
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External | 1 | X | 1 | 0 | 0 |
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*When using an external PHY replace the RPCR’s DPLX bit with the PHY’s DPLX bit.
Loopback testing is used to isolate certain blocks of the LAN91C111 by transmitting a packet, looping it back to the receiver and checking for errors. There are three different types of loopback:
EPH Loopback:
Here the packet is looped back immediately after the EPH block, or Ethernet Protocol Handler. The packet never reaches the MII bus or the internal PHY. Therefore, the PHY register settings are don’t care (RPCR DPLX, PHY LPBK). Also, in EPH loopback mode the transmitted packet is delayed before being presented to the receiver so the MAC will not see collisions. In other words, the receiver will not see the packet as it is still being transmitted which would require the MAC to be in Switched Full Duplex mode (ignores collisions). So in EPH Loopback the MAC can stay in half duplex mode.
Note: The DPLX bit in the TCR register is a don’t care. This bit is set so the MAC can receive an external packet with its own source address. Since the packet never leaves the MAC, this bit is ignored.
PHY Loopback:
The packet is sent out of the MAC, through the internal PHY and looped back at the PHY’s digital block, before it is decoded and converted to analog. In this mode the MAC and PHY must be matched for half or full duplex operation. This means the DPLX bit in the RPCR register (or the PHY’s DPLX bit for external PHYs) must match the SWFDUP bit in the MAC’s TCR register. Note that the FDUPLX bit in the TCR register must be set when in half duplex mode, to allow the MAC to receive a packet with its own source address.
Note: When the SWFDUP bit is set, the FDUPLX bit has no effect.
SMSC AN 9.6 | 33 | Revision 1.0 |
APPLICATION NOTE