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SMSC LAN91C111 3.9Burst Mode Operation Timing – Synchronous Operation

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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

nDATACS	t2
nDATACS
t3A	t4
Read Data	Valid
	t6A
t1	t5
nRD, nWR
Write Data	t5A
Write Data	D0-D31 Valid

Figure 3.8 Asynchronous Cycle - nADS=0

(nDATACS Used to Select Data Register; Must Be 32 Bit Access)

	PARAMETER	MIN	TYP	MAX	UNITS

t1	nDATACS Setup to nRD, nWR	2			ns
	Active

t2	nDATACS Hold After nRD, nWR	5			ns
	Inactive (Assuming nADS Tied
	Low)

t3A	nRD Low to Valid Data			30	ns

t4	nRD High to Data Invalid	2		15	ns

t5	Data Setup to nWR Inactive	10			ns

t5A	Data Hold After nWR Inactive	5			ns

t6A	nRD Strobe Width	30			ns

This timing diagram and subsequent parameter information detail a typical reads or write operation. As you can see by the timing diagram the first step is to have the address qualified with the assertion of nADS. Since this discussion is focused on the use of the nDATACS signal, this step is accomplished by programming the pointer register to where the access is going to occur. By using nDATACS the values on the address bus and the byte enable lines (BE0-BE3) are ignored.

There is a minimum delay of 2nS prior to the assertion of nRD or nWR. For a read operation the data becomes valid on the data bus a maximum of 30nS after the assertion of the nRD line. For a write operation the data needs to be valid for a minimum of 10nS prior to the de-assertion of nWR and needs to be held for 5nS after this de-assertion.

In asynchronous mode of operation, to accomplish multiple back-to-back transfers (either nWR or nRD) the minimum time between transactions is 80nS. This means that you can pulse either nWR or nRD at 80nS intervals. In the case of full duplex mode the timing changes to 100nS between pulses.

3.9Burst Mode Operation Timing – Synchronous Operation

Burst mode operations using the LAN91C111 require that the nVLBUS pin to be de-asserted and that an LCLK be provided. The nCYCLE pin is used to indicate that bursting is to be done and the

SMSC AN 9.6

17

Revision 1.0 (08-14-08)

APPLICATION NOTE

Contents

1 Overview 1.1Audience 2 Introduction Page 3 Description Of Bus Interface Unit (BIU) 3.2ISA Bus 3.38-BitBus 3.3.1Address Decoding Example 3.3.2I/O Base Address 300h Decoding 3.4Asynchronous Interface 3.4.1Typical Signal Connection with Asynchronous Buses 3.4.2Signal Connection with Asynchronous Interfacing 3.5Synchronous Interface (VL-Bus) 3.5.1Typical Connection with Synchronous Interface (VL-Bus) 3.5.2Signal Connection with Synchronous Interfacing LAN91C111 3.5.3Address Bus 3.5.4AEN 3.5.5W/NR 3.5.6NRDYRTN 3.5.7NSRDY 3.5.8LCLK – Clock Input 3.5.9Reset 3.5.10 NBE0-NBE3 3.6Timing Analysis 3.6.1Write Cycle Address Phase - Cycle Start 3.6.2Write Cycle Data Phase - Cycle End 3.6.3Read Cycle 3.6.4Read Cycle Address Phase – Cycle Start 3.6.5Read Cycle Delay Phase 3.6.6Read Cycle Data Phase – Cycle End 3.7Direct Data Register Access interface (nDATACS) 3.7.1The Use of NDATACS 3.7.2Pointer Register 3.7.3Data Register 3.7.4Timing Analysis Of Direct Access 3.8Asynchronous Read or Write Operation – Non Burst 3.9Burst Mode Operation Timing – Synchronous Operation 3.10 Burst Mode Write Operation 3.11 Burst Mode Read Operation 3.12 LAN91C111 Bus Interface 3.13 Sample Routine of Performance Measurement and Tuning Flow Chart 4 System Hardware Design 4.1Quartz Crystal 4.2Clock Oscillator 4.3X25OUT 4.4Serial EEPROM Operation 4.4.1INDIVIDUAL ADDRESS 20-22hex 4.4.2Use the Serial EEPROM as an Option 4.4.3How to Change the IOBASE Address 4.5Power Supply Decoupling 4.6System Power Consumption 4.7Auto Negotiation 4.7.1Initialization Sequence Steps Page 4.9Loopback 4.9.1EPH Internal Loopback (MAC) 4.9.2Diagnostic Loopback 4.9.3External Loopback Page 4.10 LED Operation 4.10.1LED Description 4.11 Thermal Information 5 Memory Management Unit - Features and Benefits 5.1Memory Partitioning 6 Big and Little Endian Issues on the LAN91C111 6.1Introduction 6.2Definition 6.2.1Big Endian 6.2.2Little Endian 6.3Implications for the LAN91C111 6.4Physical connections for Big Endian Page 6.5Software Considerations for Big Endian 6.6Source Code Example Page 6.6.1Conclusion 7 Physical Layer and Magnetics 7.1Transmit / Receive Interface 7.1.1Transmit Interface 7.1.2Receive Interface 7.1.3Magnetics 7.2RBIAS 7.2.1RBIAS pin 7.2.2TP Transmit Output Current Set 7.2.3Cable Selection 7.2.4Transmitter Droop 7.3MII Management Functions 7.3.1Example Routines To Read and Write the PHY Registers Page Page Page 7.4Multiple Register Access 8 Reset Operation 9 Functional Test and Diagnostic 9.1MAC Register Test 9.2RAM Buffer Test 9.3Transmitting A Packet 9.4Releasing The Transmitted Packet 9.5Receiving A Packet 9.6Releasing A Received Packet 9.7EPH Loopback Test 9.8PHY Loopback Test 9.9External Loopback Test 9.10 MMU Test Page 10 Migrating From LAN91C100FD and LAN83C183 to LAN91C111 10.1 91C111 Overview 10.2 New Features and Modification 10.2.1 Receive/PHY Control Register 10.2.2Memory Information Register 10.2.3 RX_OVRN bit 10.2.4 MDINT Interrupt bit 10.2.5Internal PHY Registers 10.2.6Media Independent Interface (MII) 10.2.7 Power Management 10.2.8Internal PHY and External PHY Selection 10.2.9 General Purpose Output 10.2.10 Reset 10.2.11 Interrupt Pin (INTR0) 10.2.12 SRAM Interface 10.2.13X25OUT Clock Output Pin 11 Design and Layout Check Guidelines