SMSC LAN91C111 3.11 Burst Mode Read Operation

SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

This timing diagram examples and details a burst mode write operation. The nDATACS pin remains asserted throughout the cycle and the nCYCLE pin is used to control the burst data. As long as nCYCLE remains asserted, data can be written on each rising edge of LCLK.

In the above timing diagram nRDYRTN is used to insert a wait state between the second and third data packet. The assertion of nRDYRTN is required at a minimum of 10nS before the falling edge of LCLK to insert the wait state. A wait state will be held as long as nRDYRTN remains asserted. In the above example a single wait cycle is inserted between the second and third packet of data. More wait states can be inserted by holding nRDYRTN asserted for another LCLK cycle. nRDYRTN only needs to remain asserted for 10nS after the falling edge of LCLK. Once the state machine sees the asserted nRDYRTN it will automatically insert the wait state.

Data is written on the rising edge of LCLK and needs to be stable 15nS prior to this rising edge. Data also needs to remain stable for 4nS after the rising edge to ensure that the data was properly written.

By using the Auto-Increment mode of operation it is possible to completely fill the FIFO’s with minimum overhead to the system. Once a write operation is started you can simply pump data into the FIFO’s for transmission out the Ethernet port.

3.11 Burst Mode Read Operation

The timing diagram below details a burst mode read operation and shows three separate packets of data being transferred. In this example there is a delay between the first and second packet of data being read. This delay is being accomplished using the nRDYRTN signal as in the Burst Mode Write Operation.

t17t12t14

Clock

t12A

nDATACS

t17A

W /nR nCYCLE

	t19		t19
ead Data	a	b	c
		t15
nRDYRTN

Figure 3.10 Burst Mode Read Operation

	PARAMETER		MIN	TYP	MAX	UNITS
			MIN	TYP	MAX	UNITS

t12	nDATACS Setup to LCLK Rising		20			ns

t12A	nDATACS Hold after LCLK Rising		0			ns

t14	nRDYRTN Setup to LCLK Falling		10			ns

SMSC AN 9.6		19			Revision 1.0 (08-14-08)

APPLICATION NOTE

Contents

1 Overview 1.1Audience 2 Introduction Page 3 Description Of Bus Interface Unit (BIU) 3.2ISA Bus 3.38-BitBus 3.3.1Address Decoding Example 3.3.2I/O Base Address 300h Decoding 3.4Asynchronous Interface 3.4.1Typical Signal Connection with Asynchronous Buses 3.4.2Signal Connection with Asynchronous Interfacing 3.5Synchronous Interface (VL-Bus) 3.5.1Typical Connection with Synchronous Interface (VL-Bus) 3.5.2Signal Connection with Synchronous Interfacing LAN91C111 3.5.3Address Bus 3.5.4AEN 3.5.5W/NR 3.5.6NRDYRTN 3.5.7NSRDY 3.5.8LCLK – Clock Input 3.5.9Reset 3.5.10 NBE0-NBE3 3.6Timing Analysis 3.6.1Write Cycle Address Phase - Cycle Start 3.6.2Write Cycle Data Phase - Cycle End 3.6.3Read Cycle 3.6.4Read Cycle Address Phase – Cycle Start 3.6.5Read Cycle Delay Phase 3.6.6Read Cycle Data Phase – Cycle End 3.7Direct Data Register Access interface (nDATACS) 3.7.1The Use of NDATACS 3.7.2Pointer Register 3.7.3Data Register 3.7.4Timing Analysis Of Direct Access 3.8Asynchronous Read or Write Operation – Non Burst 3.9Burst Mode Operation Timing – Synchronous Operation 3.10 Burst Mode Write Operation 3.11 Burst Mode Read Operation 3.12 LAN91C111 Bus Interface 3.13 Sample Routine of Performance Measurement and Tuning Flow Chart 4 System Hardware Design 4.1Quartz Crystal 4.2Clock Oscillator 4.3X25OUT 4.4Serial EEPROM Operation 4.4.1INDIVIDUAL ADDRESS 20-22hex 4.4.2Use the Serial EEPROM as an Option 4.4.3How to Change the IOBASE Address 4.5Power Supply Decoupling 4.6System Power Consumption 4.7Auto Negotiation 4.7.1Initialization Sequence Steps Page 4.9Loopback 4.9.1EPH Internal Loopback (MAC) 4.9.2Diagnostic Loopback 4.9.3External Loopback Page 4.10 LED Operation 4.10.1LED Description 4.11 Thermal Information 5 Memory Management Unit - Features and Benefits 5.1Memory Partitioning 6 Big and Little Endian Issues on the LAN91C111 6.1Introduction 6.2Definition 6.2.1Big Endian 6.2.2Little Endian 6.3Implications for the LAN91C111 6.4Physical connections for Big Endian Page 6.5Software Considerations for Big Endian 6.6Source Code Example Page 6.6.1Conclusion 7 Physical Layer and Magnetics 7.1Transmit / Receive Interface 7.1.1Transmit Interface 7.1.2Receive Interface 7.1.3Magnetics 7.2RBIAS 7.2.1RBIAS pin 7.2.2TP Transmit Output Current Set 7.2.3Cable Selection 7.2.4Transmitter Droop 7.3MII Management Functions 7.3.1Example Routines To Read and Write the PHY Registers Page Page Page 7.4Multiple Register Access 8 Reset Operation 9 Functional Test and Diagnostic 9.1MAC Register Test 9.2RAM Buffer Test 9.3Transmitting A Packet 9.4Releasing The Transmitted Packet 9.5Receiving A Packet 9.6Releasing A Received Packet 9.7EPH Loopback Test 9.8PHY Loopback Test 9.9External Loopback Test 9.10 MMU Test Page 10 Migrating From LAN91C100FD and LAN83C183 to LAN91C111 10.1 91C111 Overview 10.2 New Features and Modification 10.2.1 Receive/PHY Control Register 10.2.2Memory Information Register 10.2.3 RX_OVRN bit 10.2.4 MDINT Interrupt bit 10.2.5Internal PHY Registers 10.2.6Media Independent Interface (MII) 10.2.7 Power Management 10.2.8Internal PHY and External PHY Selection 10.2.9 General Purpose Output 10.2.10 Reset 10.2.11 Interrupt Pin (INTR0) 10.2.12 SRAM Interface 10.2.13X25OUT Clock Output Pin 11 Design and Layout Check Guidelines