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SMSC LAN91C111 4.2Clock Oscillator, 4.3X25OUT, 4.4Serial EEPROM Operation

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SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

			LIMIT

SYMBOL	PARAMETER	MIN.	TYPICAL	MAX.	UNIT

t2	Xtal1 High Time	18			ns

t3	Xtal1 Low time	18			ns

It‘s not recommend to implement PLL clock parts with LAN91C111. The device is very sensitive to PLL clock jitters, which may cause startup and link problems.

4.2Clock Oscillator

If an external clock is used, it should be connected to the input of the amplifier (XTAL1). If an oscillator is to be used, leave XTAL2 floating. Driving XTAL2 could cause problems due to high gain and high current.

Oscillator Specifications

Parameter	Spec
Frequency	25 Mhz ± 50 ppm
Duty Cycle	45% to 55%
Output Load	10 TTL Max.

Oscillator components should be mounted as close to the chip and have short, direct traces to XTAL1, XTAL2, and VSS pins. Noise arriving at XTAL1 or XTAL2 pins can cause a miscount in the internal clock-generating circuitry. These kinds of glitches can be produced through capacitive coupling between the oscillator components and PCB traces carrying digital signals with fast rise and fall times. It is also recommended not to run any high-speed signals below the area of the crystal circuitry. Hand layout for this area of the board is recommended.

4.3X25OUT

X25OUT is 25Mhz-clock source provided by the LAN91C111 for an external PHY to eliminate the need for an extra crystal or oscillator. This pin can be directly connected the clock oscillator input of the external PHY. This clock source pin is active during reset.

4.4Serial EEPROM Operation

The LAN91C111 supports a serial EEPROM interface. The EEPROM holds the following parameters:

1.Ethernet Individual Address

2.I/O Base Address

3.MII Interface

All of the above mentioned values are read from the EEPROM upon hardware reset. Except for the INDIVIDUAL ADDRESS, the value of the IOS switches determines the offset within the EEPROM for

Revision 1.0 (08-14-08)

24

SMSC AN 9.6

APPLICATION NOTE

Contents

1 Overview 1.1Audience 2 Introduction Page 3 Description Of Bus Interface Unit (BIU) 3.2ISA Bus 3.38-BitBus 3.3.1Address Decoding Example 3.3.2I/O Base Address 300h Decoding 3.4Asynchronous Interface 3.4.1Typical Signal Connection with Asynchronous Buses 3.4.2Signal Connection with Asynchronous Interfacing 3.5Synchronous Interface (VL-Bus) 3.5.1Typical Connection with Synchronous Interface (VL-Bus) 3.5.2Signal Connection with Synchronous Interfacing LAN91C111 3.5.3Address Bus 3.5.4AEN 3.5.5W/NR 3.5.6NRDYRTN 3.5.7NSRDY 3.5.8LCLK – Clock Input 3.5.9Reset 3.5.10 NBE0-NBE3 3.6Timing Analysis 3.6.1Write Cycle Address Phase - Cycle Start 3.6.2Write Cycle Data Phase - Cycle End 3.6.3Read Cycle 3.6.4Read Cycle Address Phase – Cycle Start 3.6.5Read Cycle Delay Phase 3.6.6Read Cycle Data Phase – Cycle End 3.7Direct Data Register Access interface (nDATACS) 3.7.1The Use of NDATACS 3.7.2Pointer Register 3.7.3Data Register 3.7.4Timing Analysis Of Direct Access 3.8Asynchronous Read or Write Operation – Non Burst 3.9Burst Mode Operation Timing – Synchronous Operation 3.10 Burst Mode Write Operation 3.11 Burst Mode Read Operation 3.12 LAN91C111 Bus Interface 3.13 Sample Routine of Performance Measurement and Tuning Flow Chart 4 System Hardware Design 4.1Quartz Crystal 4.2Clock Oscillator 4.3X25OUT 4.4Serial EEPROM Operation 4.4.1INDIVIDUAL ADDRESS 20-22hex 4.4.2Use the Serial EEPROM as an Option 4.4.3How to Change the IOBASE Address 4.5Power Supply Decoupling 4.6System Power Consumption 4.7Auto Negotiation 4.7.1Initialization Sequence Steps Page 4.9Loopback 4.9.1EPH Internal Loopback (MAC) 4.9.2Diagnostic Loopback 4.9.3External Loopback Page 4.10 LED Operation 4.10.1LED Description 4.11 Thermal Information 5 Memory Management Unit - Features and Benefits 5.1Memory Partitioning 6 Big and Little Endian Issues on the LAN91C111 6.1Introduction 6.2Definition 6.2.1Big Endian 6.2.2Little Endian 6.3Implications for the LAN91C111 6.4Physical connections for Big Endian Page 6.5Software Considerations for Big Endian 6.6Source Code Example Page 6.6.1Conclusion 7 Physical Layer and Magnetics 7.1Transmit / Receive Interface 7.1.1Transmit Interface 7.1.2Receive Interface 7.1.3Magnetics 7.2RBIAS 7.2.1RBIAS pin 7.2.2TP Transmit Output Current Set 7.2.3Cable Selection 7.2.4Transmitter Droop 7.3MII Management Functions 7.3.1Example Routines To Read and Write the PHY Registers Page Page Page 7.4Multiple Register Access 8 Reset Operation 9 Functional Test and Diagnostic 9.1MAC Register Test 9.2RAM Buffer Test 9.3Transmitting A Packet 9.4Releasing The Transmitted Packet 9.5Receiving A Packet 9.6Releasing A Received Packet 9.7EPH Loopback Test 9.8PHY Loopback Test 9.9External Loopback Test 9.10 MMU Test Page 10 Migrating From LAN91C100FD and LAN83C183 to LAN91C111 10.1 91C111 Overview 10.2 New Features and Modification 10.2.1 Receive/PHY Control Register 10.2.2Memory Information Register 10.2.3 RX_OVRN bit 10.2.4 MDINT Interrupt bit 10.2.5Internal PHY Registers 10.2.6Media Independent Interface (MII) 10.2.7 Power Management 10.2.8Internal PHY and External PHY Selection 10.2.9 General Purpose Output 10.2.10 Reset 10.2.11 Interrupt Pin (INTR0) 10.2.12 SRAM Interface 10.2.13X25OUT Clock Output Pin 11 Design and Layout Check Guidelines