Manuals / Brands / Computer Equipment / Network Card / SMSC / Computer Equipment / Network Card

SMSC LAN91C111 3.5.1Typical Connection with Synchronous Interface (VL-Bus)

1 60

Download 60 pages, 677.02 Kb

SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

3.5.1Typical Connection with Synchronous Interface (VL-Bus)

HOST (VL BUS)	LAN91C111
SIGNAL	SIGNAL					NOTES

A2-A15	A2-A15		Address bus used for I/O space and register
			decoding, latched by nADS rising edgeand
			transparent on nADS low time.

M/nIO	AEN		Qualifies valid I/O decoding - enabled access
			when low. This signal is latched by nADS rising
			edge and transparent on nADS low time.

W/nR	W/nR		Direction of access. Sampled by the
			LAN91C111 on first rising clock that has
			nCYCLE active. High on writes, low on reads.

nRDYRTN	nRDYRTN		Ready return. Direct connection to VL bus.

nLRDY	nSRDY and some		nSRDY has the appropriate functionality and
	logic		timing to create the VL nLRDY except that
			nLRDY behaves like an open drain output most
			of the time.

LCLK	LCLK		Local Bus Clock. Rising edges used for
			synchronous bus interface transactions.

nRESET	RESET		Connected via inverter to the LAN91C111.

nBE0 nBE1 nBE2 nBE3	nBE0 nBE1 nBE2		Byte enables. Latched transparently by nADS
	nBE3		rising edge.

nADS	nADS, nCYCLE		Address Strobe is connected directly to the VL
			bus. nCYCLE is created typically by using
			nADS delayed by one LCLK.

IRQn	INTR0		Typically uses the interrupt lines on the ISA
			edge connector of VL bus

D0-D31	D0-D31		32 bit data bus. The bus byte(s) used to access
			the device are a function of nBE0-nBE3:
			nBE0	nBE1	nBE2		nBE3
			0	0	0	0			Double word access
			0	0	1	1			Low word access
			1	1	0	0			High word access
			0	1	1	1			Byte 0 access
			1	0	1	1			Byte 1 access
			1	1	0	1			Byte 2 access
			1	1	1	0			Byte 3 access
			Not used = tri-state on reads, ignored on writes.
			Note that nBE2 and nBE3 override the value of
			A1, which is tied low in this application.

nLDEV	nLDEV		nLDEV is a totem pole output. nLDEV is active
			on valid decodes of A15-A4 and AEN=0.

	UNUSED PINS

VCC	nRD nWR		Pull up externally (May through 10KΩ resistor)

GND	A1 nVLBUS		Pull down externally (May through 10KΩ
			resistor)

OPEN	nDATACS		Leave Open

Revision 1.0 (08-14-08)	8								SMSC AN 9.6

APPLICATION NOTE

Contents

1 Overview 1.1Audience 2 Introduction Page 3 Description Of Bus Interface Unit (BIU) 3.2ISA Bus 3.38-BitBus 3.3.1Address Decoding Example 3.3.2I/O Base Address 300h Decoding 3.4Asynchronous Interface 3.4.1Typical Signal Connection with Asynchronous Buses 3.4.2Signal Connection with Asynchronous Interfacing 3.5Synchronous Interface (VL-Bus) 3.5.1Typical Connection with Synchronous Interface (VL-Bus) 3.5.2Signal Connection with Synchronous Interfacing LAN91C111 3.5.3Address Bus 3.5.4AEN 3.5.5W/NR 3.5.6NRDYRTN 3.5.7NSRDY 3.5.8LCLK – Clock Input 3.5.9Reset 3.5.10 NBE0-NBE3 3.6Timing Analysis 3.6.1Write Cycle Address Phase - Cycle Start 3.6.2Write Cycle Data Phase - Cycle End 3.6.3Read Cycle 3.6.4Read Cycle Address Phase – Cycle Start 3.6.5Read Cycle Delay Phase 3.6.6Read Cycle Data Phase – Cycle End 3.7Direct Data Register Access interface (nDATACS) 3.7.1The Use of NDATACS 3.7.2Pointer Register 3.7.3Data Register 3.7.4Timing Analysis Of Direct Access 3.8Asynchronous Read or Write Operation – Non Burst 3.9Burst Mode Operation Timing – Synchronous Operation 3.10 Burst Mode Write Operation 3.11 Burst Mode Read Operation 3.12 LAN91C111 Bus Interface 3.13 Sample Routine of Performance Measurement and Tuning Flow Chart 4 System Hardware Design 4.1Quartz Crystal 4.2Clock Oscillator 4.3X25OUT 4.4Serial EEPROM Operation 4.4.1INDIVIDUAL ADDRESS 20-22hex 4.4.2Use the Serial EEPROM as an Option 4.4.3How to Change the IOBASE Address 4.5Power Supply Decoupling 4.6System Power Consumption 4.7Auto Negotiation 4.7.1Initialization Sequence Steps Page 4.9Loopback 4.9.1EPH Internal Loopback (MAC) 4.9.2Diagnostic Loopback 4.9.3External Loopback Page 4.10 LED Operation 4.10.1LED Description 4.11 Thermal Information 5 Memory Management Unit - Features and Benefits 5.1Memory Partitioning 6 Big and Little Endian Issues on the LAN91C111 6.1Introduction 6.2Definition 6.2.1Big Endian 6.2.2Little Endian 6.3Implications for the LAN91C111 6.4Physical connections for Big Endian Page 6.5Software Considerations for Big Endian 6.6Source Code Example Page 6.6.1Conclusion 7 Physical Layer and Magnetics 7.1Transmit / Receive Interface 7.1.1Transmit Interface 7.1.2Receive Interface 7.1.3Magnetics 7.2RBIAS 7.2.1RBIAS pin 7.2.2TP Transmit Output Current Set 7.2.3Cable Selection 7.2.4Transmitter Droop 7.3MII Management Functions 7.3.1Example Routines To Read and Write the PHY Registers Page Page Page 7.4Multiple Register Access 8 Reset Operation 9 Functional Test and Diagnostic 9.1MAC Register Test 9.2RAM Buffer Test 9.3Transmitting A Packet 9.4Releasing The Transmitted Packet 9.5Receiving A Packet 9.6Releasing A Received Packet 9.7EPH Loopback Test 9.8PHY Loopback Test 9.9External Loopback Test 9.10 MMU Test Page 10 Migrating From LAN91C100FD and LAN83C183 to LAN91C111 10.1 91C111 Overview 10.2 New Features and Modification 10.2.1 Receive/PHY Control Register 10.2.2Memory Information Register 10.2.3 RX_OVRN bit 10.2.4 MDINT Interrupt bit 10.2.5Internal PHY Registers 10.2.6Media Independent Interface (MII) 10.2.7 Power Management 10.2.8Internal PHY and External PHY Selection 10.2.9 General Purpose Output 10.2.10 Reset 10.2.11 Interrupt Pin (INTR0) 10.2.12 SRAM Interface 10.2.13X25OUT Clock Output Pin 11 Design and Layout Check Guidelines