SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller

4.8Power up / Initialization and Powerdown Mode

When the LAN91C111 powers up or resets, the internal PHY enters the following modes.

1.Isolation Mode

2.Manual Mode (AutoNegotiation Off)

3.10Mbps

4.Half Duplex

When the internal PHY is placed in isolation mode, the internal PHY is able to respond to management transactions, such as reading / writing the PHY registers. But the internal MII will not respond to the transmit signals and presents a high impedance on the receive data signals to the MAC, and will not send link pulses to the remote device to establish link. The internal PHY can leave isolation mode by simply clear the MII_DIS bit in the PHY MI Serial Port Control Register. After the MII_DIS bit is cleared, the internal MII is able to respond to transmit, and receive signals, and the internal PHY will immediately send out link pulses to the remote device to establish link.

The LAN91C111 supports vary power-down states. The internal PHY can be placed in a low-power consumption state by setting the PDN bit in the PHY MI Serial Port Control Register. Clearing this bit to zero allows normal operation. The EPH POWER EN bit in the MAC Configuration Register is used to selectively power transition the EPH to a low power mode. When this bit is cleared (0), the Host will place the EPH into a low power mode. The Ethernet MAC will gate the 25Mhz TX and RX clock so that the Ethernet MAC will no longer be able to receive and transmit packets. The Host interface however, will still be active allowing the Host accesses to the device through Standard IO access. All LAN91C111 registers will still be accessible. However, status and control will not be allowed until the EPH POWEREN bit is set and a RESET MMU command is initiated. Please use the power management algorithm described in section 8.1 in the LAN91C111 datasheet to handle power management.

4.9Loopback

Loopback mode is intended for system diagnostics. The controller must enable transmit and receive to allow the controller to receive its own packets. The LAN91C111 supports three types of loopback modes.

4.9.1EPH Internal Loopback (MAC)

The internal MAC supports EPH internal loopback. Serial data is internally looped back at EPH block when EPH _LOOP bit is set in the Transmit Control Register, it also disable transmit output and receive input of the Media Independent Interface. The management interface of the MII is still active for accessing the PHY registers.

SMSC AN 9.6

31

Revision 1.0 (08-14-08)

APPLICATION NOTE