SMSC LAN91C111
4 System Hardware Design
The LAN91C111 fully integrates the MAC, PHY, and SRAM into a single chip. It requires a minimum number of external components to complete the system design. For example, it requires only a transformer, an oscillator, some resistors, capacitors, and an optional EEPROM to complete a standard ISA system design. For other embedded processor systems, some processors have address decode generation logic internal to the microcontroller; the system designer should do a complete timing analysis and add external logic between the host and the Bus Interface Unit of the LAN91C111 as necessary. As outlined in previous sections of this manual, external logic is system dependant.
4.1Quartz Crystal
The LAN91C111 contains
Crystal Specifications
PARAMETER | SPEC |
Type | Parallel Resonant |
Frequency | 25MHz ± 50 ppm |
Duty Cycle | 45% to 55% |
Equivalent | Series Resistance 40Ω max |
Load Capacitance | 20pF typical |
Case Capacitance | 7 pf maximum |
Power Dissipation | 1 mW maximum |
Crystal components should be mounted as close to the chip and have short, direct traces to XTAL1, XTAL2, and VSS pins. Noise arriving at XTAL1 or XTAL2 pins can cause a miscount in the internal
A serial resistor with value of 10W~30W may be suggested to add in serial with the XTAL2 pin of LAN91C111 as shown in Figure 3.2, which can guarantee ( and may reduce) the maximum input voltage not exceed the recommended level; This may also reduce the EMI affection on the Crystal oscillator circuitry. The value of this serial resistor must be verified through Lab experiments.
A 1M Ohm resistor is recommended to be connected between XTAL1 and XTAL2 to improve the startup link for some crystal oscillators.
25Mhz Clock Xtal1 Signal:
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SYMBOL | PARAMETER | MIN. | TYPICAL | MAX. | UNIT |
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t1 | Clock cycle period | 39,998 | 40 | 40.002 | ns |
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SMSC AN 9.6 |
| 23 |
| Revision 1.0 |
APPLICATION NOTE