BIOS SETUP
Advanced Chipset Features
This Setup menu controls the configuration of the chipset.
CMOS Setup Utility – Copyright ©
Advanced Chipset Features
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| DRAM Timing Selectable | By SPD | ITEM HELP |
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| CAS Latency Time | 2.5 | Menu Level |
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| Active to Precharge Delay | 7 |
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| DRAM RAS# to CAS# Delay | 3 |
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| DRAM RAS# Precharge | 3 |
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| DRAM Data Integrity Mode |
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| Memory Frequency For | Auto |
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| DRAM Read Thermal Mgmt | Disabled |
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| System BIOS Cacheable | Enabled |
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| Video BIOS Cacheable | Enabled |
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| Video RAM Cacheable | Disabled |
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| Memory Hole At | Disabled |
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| Delayed Transaction | Enabled |
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| Delay Prior to Thermal | 16 Min |
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| AGP Aperture Size (MB) | 64 |
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| ICH2 ISA Enable | Enabled |
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DRAM Timing Selectable
This option refers to the method by which the DRAM timing is selected. The default is By SPD.
CAS Latency Time
You can select CAS latency time in HCLKs of 2/2 or 3/3. The system board designer should set the values in this field, depending on the DRAM installed. Do not change the values in this field unless you change specifications of the installed DRAM or the installed CPU. The choices are 2 and 3.
Active to Precharge Delay
The default setting for the Active to Precharge Delay is 6.
DRAM RAS# to CAS# Delay
This option allows you to insert a delay between the RAS (Row Address Strobe) and CAS (Column Address Strobe) signals. This delay occurs when the SDRAM is written to, read from or refreshed. Reducing the delay improves the performance of the SDRAM.
DRAM RAS# Precharge
This option sets the number of cycles required for the RAS to accumulate its charge before the SDRAM refreshes. The default setting for the Active to Precharge Delay is 3.
IB810 User’s Manual | 37 |
