SUPER MICRO Computer AS1011M-T2 SouthBridge/MCP55 Configuration, ECC Configuration DRAM ECC Enable

AS1011M-T2 User's Manual

ECC Configuration

DRAM ECC Enable

DRAM ECC allows hardware to report and correct memory errors automati- cally. Options are Enabled and Disabled.

4-Bit ECC Mode

Allows the user to enabled 4-bit ECC mode (also known as ECC Chip- kill). Options are Enabled and Disabled.

DRAM Scrub Redirect

Allows system to correct DRAM ECC errors immediately, even with background scrubbing on. Options are Enabled and Disabled.

DRAM BG Scrub

Corrects memory errors so later reads are correct. Options are Dis- abled and various times in nanoseconds and microseconds.

L2 Cache BG Scrub

Allows L2 cache RAM to be corrected when idle. Options are Disabled and various times in nanoseconds and microseconds.

Data Cache BG Scrub

Allows L1 cache RAM to be corrected when idle. Options are Disabled and various times in nanoseconds and microseconds.

Power Down Control

Allows DIMMs to enter power down mode by deasserting the clock enable signal when DIMMs are not in use. Options are Auto and Disabled.

Alternate VID

Specify the alternate VID while in low power states. Options are various voltages from .8V to 1.050V in increments of .025V. Default setting is 0.850V.

SouthBridge/MCP55 Configuration

CPU/LDT Spread Spectrum

Use this setting to choose Center Spread, Down Spread or to Disable spread spectrum for the CPU/LDT. Spread Spectrum is a method of reducing the

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