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13.3 PCCC

Ethernet-enabled Allen-Bradley legacy PLCs (such as the PLC5E and SLC- 5/05 series) use a protocol called PCCC (Programmable Controller Communication Commands) to communicate over the Ethernet network. The interface card supports PCCC for direct connectivity to these PLCs.

If a connection timeout or socket-level error occurs, the driver will trigger a timeout event as described in section 10.7.4.

13.3.1 Tag Reference

Register contents are read from and written to the interface card via PCCC by reference to an integer “file/section number” and an “offset/element” within that file. Reading is performed via the PCCC “PLC5 Read” (DF1 protocol typed read) service, and writing is performed via the PCCC “PLC5 Write” (DF1 protocol typed write) service.

The formula to calculate which register is targeted in the interface card is provided in Equation 3.

target register = (file number -10)100 + offset

Equation 3

In Equation 3, “target register” [1…1485], “file number” [10…24] (which means N10…N24), and “offset” is restricted only by the limitations of the programming software (but is a value of 1485 max). Table 5 provides some examples of various combinations of file/section numbers and offsets/elements which can be used to access drive registers. Note that there are multiple different combinations of file/section numbers and offsets/elements that will result in the same drive register being accessed.

Table 5: PCCC Target Register Examples

File/Section

 

Offset/Element

 

 

Start Target

 

Number

 

 

 

Register

 

 

 

 

 

 

N10

1

 

1

 

N12

99

 

299

 

N11

199

 

299

 

N20

7

 

1007

 

N24

85

 

1485

 

N10

1485

 

1485

 

In addition to providing access to the drive registers in their “standard” numerical locations as mentioned above, the registers can also be accessed in a special “assembly object” type format by targeting integer file N50. What this means is that when N50 is targeted for reading, what is actually returned by the interface card is the user-defined register data as ordered by the EtherNet/IP produced register configuration array (refer to section 10.8.4). Similarly, when

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