Toshiba MK1032GAX 71

Disk errors occurred during Write Multiple command are posted after the attempted disk write of the block or partial block which are transferred. The Write Multiple command is terminated at the sector in error , even if it was in the middle of a block. Subsequent blocks are not transferred after an error. Interrupts are generated for each block or each sector, when DRQ is set .

After the transfer of a data block which contains a sector with error, the contents of the Command Block Registers are undefined. The host should retry the transfer as individual requests to obtain valid error information.

Toshiba Corporation Digital Media Network Company

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Contents

1.1.1.1.1.1.1.1 TOSHIBA Revision History 2.5 inch Hard Disk Drive MK1032GAX Product Specification Revision Date Initial issue ＳＡＦＥＴＹ IMPORTANT MESSAGES LIMITATION OF LIABILITY USAGE RESTRICTIONS SAFETY Page TABLE OF CONTENTS Page Page Table of Figures MK1032GAX D 2 M ATA 4 P 2. SCOPE 3. GENERAL DESCRIPTION Page 4.KEY FEATURES 5. BASIC SPECIFICATION 6. PERFORMANCE 7. POWER REQUIREMENTS 7.1 Supply Voltage 7.2 Power Consumption 7.3 Energy Consumption Efficiency 8. MECHANICAL SPECIFICATIONS 8.1 Dimension 8.2 Weight 8.3 Drive Orientation 8.4 Mounting Instructions 8.4.1 Screwing 8.4.2 Installation Figure 1 MK1032GAX Dimensions Page Figure 2 Mounting Recommendation 9. ENVIRONMENTAL LIMITS 9.1 Temperature and Humidity 9.1.1 Temperature 9.1.2 Humidity 9.2 Vibration 9.4 Altitude 9.5 Acoustics（Sound Power） 9.6 Safety Standards 9.7 EMC Adaptability 9.8Magnetic Fields 10. RELIABILITY 10.1 Error Rate 10.1.1 Non- Recoverable Error Rate 10.1.2 Seek Error Rate 10.2 Mean Time to Failure (MTTF) 10.6 Load/Unload HOST INTERFACE 11.1 Cabling Interface Connector 11.1.2 Cable 11.2 Electrical specification 11.2.1 Cable length and capacitance 11.2.2 DC input/output Characteristics 11.2.2.1 Input 11.2.2.2 Output 11.3 Interface connector 11.3.1 ATA interface connector 11.3.2 Pin Assignment 11.3.3 Signal Treatment 11.3.4 Series resistance 11.3.5 Signal Description I/O 11.4 Host Interface Timing 11.4.1 Program I/O Write Timing 11.4.2 Program I/O Read Timing 11.4.3 Multiword DMA Write Timing 11.4.4 Multiword DMA Read Timing 11.4.5 Ultra DMA Timing Sustained Ultra DMA data in burst Host pausing an Ultra DMA data in burst Device terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst Initiating an Ultra DMA data out burst Sustained Ultra DMA data out burst Device pausing an Ultra DMA data out burst Host terminating an Ultra DMA data out burst Device terminating an Ultra DMA data out burst Page 11.4.6 Reset Timing 11.5 Grounding 11.6 Address Decoding 11.7 Register Description 11.7.1 Data Register 11.7.1.1 Read/Write command 11.7.1.2 Read/Write Buffer command 11.7.1.3 Format command 11.7.2 Error Register 11.7.2.1 Operational Mode 11.7.2.2 Diagnostic Mode 11.7.3 Features Register (Write Precompensation Register) 11.7.3.1 Smart command 11.7.4 Sector Count Register 11.7.4.1 Disk Access command 11.7.4.2 Initialize Device Parameters command 11.7.5 Sector Number Register 11.7.6 Cylinder Low Registers 11.7.6.1 Disk Access command 11.7.6.2 SMART commands 11.7.7 Cylinder High Registers 11.7.8 Device/Head Register 11.7.9 Status Register 11.7.10 Command Register Command Code Page 11.7.11 Alternate Status Register 11.7.12 Device Control Register 11.7.13 Device Address register4 11.8 Command Descriptions 11.8.1 Nop (00h) 11.8.2 Recalibrate5 (1xh) 11.8.3 Flush Cache (E7h) 11.8.4 Flush Cache EXT (EAh) 11.8.5 Read Sector 11.8.6 Read Sector EXT 11.8.7 Write Sector 11.8.8 Write Sector EXT 11.8.9 Read Verify (40h) 11.8.10 Read Verify EXT 11.8.11 Write Verify6 (3Ch) 11.8.12 Format Track Page 11.8.13 Seek (7xh) 11.8.14 Toshiba Specific 11.8.15 Execute Diagnostics (90h) 11.8.16 Initialize Device Parameters (91h) 11.8.17 Download Microcode (92h) 11.8.18 Read Multiple 11.8.19 Read Multiple EXT (29h) 11.8.20 Write Multiple Page 11.8.21 Write Multiple EXT (39h) 11.8.22 Set Multiple Mode (C6h) 11.8.23 Read DMA 11.8.24 Read DMA EXT 11.8.25 Write DMA (CAh/CBh) 11.8.26 Write DMA EXT 11.8.27 Power Control (Exh) 11.8.27.1 Stand-byImmediate (E0/94) 11.8.27.2 Idle Immediate (E1/95) 11.8.27.3 Stand-by(E2/96) 11.8.27.4 Idle (E3/97) 11.8.27.5 Check Power Mode (E5/98) 11.8.27.6 Sleep (E6/99) 11.8.28 Read Buffer (E4h) 11.8.29 Write Buffer 11.8.30Identify Device (ECh) Page Page Page Page Page Page Page Page Page Page Page Page Page Page 11.8.31 SET MAX (F9h) Set Max Address 11.8.31.2 Set Max Set Password 11.8.31.3 Set Max Lock 11.8.31.4 Set Max Unlock 11.8.31.5 Set Max Freeze Lock 11.8.32SET MAX ADDRESS EXT (37h) 11.8.33 Read Native Max Address (F8h) 11.8.34 Read Native Max Address EXT (27h) 11.8.35 Set Features (EFh) 11.8.36 SECURITY SET PASSWORD (F1h) 11.8.37 SECURITY UNLOCK (F2h) 11.8.38 SECURITY ERASE PREPARE (F3h) 11.8.39 SECURITY ERASE UNIT (F4h) 11.8.40 SECURITY FREEZE LOCK (F5h) 11.8.41 SECURITY DISABLE PASSWORD 11.8.42 SMART Function Set (B0h) SMART Read Attribute values Attribute Name Value Definition Self-testexecution status values Page SMART Read Attribute thresholds 11.8.42.3 SMART Enable Disable Attribute Autosave SMART Save Attribute Values SMART Execute Off-lineImmediate 11.8.42.5.2 Captive mode 11.8.42.5.3 SMART off-lineroutine 11.8.42.5.4 SMART Short self-testroutine 11.8.42.5.5 SMART Extended self-testroutine 11.8.42.5.6 SMART Selective self-testroutine Page SMART Read Log Sector SMART Log Directory 11.8.42.6.2 Summary error log sector SMART summary error log sector 11.8.42.6.2.1 Error log version 11.8.42.6.2.2 Error log data structure 11.8.42.6.2.3 Command data structure Command data structure 11.8.42.6.2.4 Error data structure Error data structure State field values State 11.8.42.6.2.5 Device error count 11.8.42.6.2.6 Data structure checksum 11.8.42.6.3 Comprehensive error log Comprehensive error log 11.8.42.6.3.1 Error log version 11.8.42.6.3.2 Error log index 11.8.42.6.3.3 Error log data structure 11.8.42.6.3.4 Device error count Self-testlog data structure 11.8.42.6.4.1 Self-testlog data structure revision number 11.8.42.6.4.2 Self-testlog descriptor entry Self-testlog descriptor entry 11.8.42.6.4.3 Self-testindex 11.8.42.6.4.4 Data structure checksum 11.8.42.6.5 Selective self-testlog Selective self-testlog Read/write 11.8.42.6.5.4 Current span under test 11.8.42.6.5.5 Feature flags Selective self-testfeature flags Bit 11.8.42.6.5.6 Selective self-testpending time 11.8.42.7 SMART Write Log Sector 11.8.42.8 SMART Enable Operations SMART Disable Operations SMART Return Status 11.8.42.11 SMART Enable/Disable Automatic Off-line 11.8.43 Read Log EXT (2Fh) 11.8.43.1 General Purpose Log Directory 11.8.43.2 Extended Comprehensive SMART Error log 11.8.43.2.3 Extended Error log data structure Extended Error log data structure 11.8.43.2.3.1 Command data structure Command data structure 11.8.43.2.3.2 Error data structure Error data structure State field values State 11.8.43.2.4 Device error count 11.8.43.3 Extended Self-testlog sector Extended Self-testlog descriptor entry 11.8.43.3.4 Data structure checksum 11.8.44 Write Log EXT (3Fh) 11.8.45 Device Configuration (B1h) 11.8.45.1 Device Configuration Restore Device Configuration Freeze Lock Device Configuration Identify 11.8.45.3.1.1 Word 0: Data structure revision 11.8.45.3.1.2 Word 1: Multiword DMA modes supported 11.8.45.3.1.3 Word 2: Ultra DMA modes supported 11.8.45.3.1.4 Words 3-6:Maximum LBA address Device Configuration Set 11.8.45.4.1 Error outputs Register 11.8.45.4.2 Description 11.8.45.4.2.1 Word 0: Data structure revision 11.8.45.4.2.2 Word 1: Multiword DMA modes supported 11.8.45.4.2.3 Word 2: Ultra DMA modes supported 11.8.45.4.2.4 Words 3-6:Maximum LBA address 11.8.45.4.2.5 Word 7: Command/features set supported 11.8.45.4.2.6Words 8-254:Reserved 11.8.45.4.2.7Word 255: Integrity word 11.9 Security Mode Feature Set 11.9.1 Security mode default setting 11.9.2 Initial setting of the user password 11.9.3 Security mode operation from power-on 11.9.4 Password lost 11.9.5 Command Table 11.10 Self-Monitoring,Analysis and Reporting Technology 11.10.1Attributes 11.10.2 Attributes values 11.10.3 SMART function default setting Page 11.11 Adaptive Power Mode Control 11.11.1 Performance Idle 11.11.2 Active Idle 11.11.3Low Power Idle 11.11.4Transition time 11.12 Reset 11.13 Drive0/Drive1 Configuration 11.14 Cache Memory 11.14.1 Cache Operations 11.14.2 Notes for write cache 11.15 Automatic Write Reallocation 12. Protocol 12.1 PIO data in commands 12.2 PIO data out commands 12.3 Non-datacommands Page 12.4 DMA data transfer commands 12.5 Ultra DMA Page Page 12.6 Other timings