1
Bad
N
Bad image- Horizontal bands or lines
N
Bad image-
Corrupted color ramp test image
N
Bad
Y1. Check DMD elastomer interconnect 2. Check DMD data outputs from DPF2A ASIC(U77)
1. Check DMD elastomer interconnect
Y2. Check outputs from DMDSR16C(U88)
3. Check input voltages to DMDSR16C
4.Replace DMD or DMDSR16C if needed
5.Check VCC2 Voltage is 7.5V
|
| 1. | Check interconnect on data inputs GY(8:0), |
|
|
| RV(7:0),BU(7:0) |
Y | 2. | Check color wheel alignment | |
3. Check CWINDEX has only one rising edge | |||
|
|
| transition per color wheel revolution |
|
| 4. | Check color wheel is running in correct |
|
|
| direction |
|
| 5. | Verify sequence version is correct from |
|
|
| color wheel |
|
| 6. | Verify flash checksum |
|
| 7. | Verify the color wheel is runing at correct |
|
|
| |
|
|
|
|
Y1. Check data interconnect between SDRAMs and DPF2A ASIC
2.Replace SDRAM(U78~U81) or DPF2A if needed
N
Bad
N
2
1. Check address and control signal
Yinterconnects between FPGA(U76) and the SDRAMs
2.Replace FPGA or SDRAMS if needed
*The flicker is caused by one SDRAM
bank displaying bad data and the other bank displaying good data. This results in bad data displayed every other frame. The freeze command stops the SDRAM buffers(A&B) from toggling between read
&write. This is useful in seeing the output from one SDRAM bank at a time
40