Intel 536EX manual 9.2.1Scratch Register SCR, 9.2.2Modem Status Register MSR, Intel Confidential

Page 95
9.2.1Scratch Register (SCR)

Parallel Host Interface 16C450/16C550A UART

9.2UART Register Definitions

9.2.1Scratch Register (SCR)

Figure 14. Scratch Register (SCR)

Register 7

SCR

This is an 8-bit read/write register used by the DTE for temporary storage of data.

9.2.2Modem Status Register (MSR)

Figure 15. Modem Status Register (MSR)

Register 6

DCD

RI

DSR

CTS

DDCDD

TERI

DDSR

DCTS

This register provides four bits (bits 7:4) that show current modem state and four bits (bits 3:0) that provide modem change information. Bits 3:0 are set to ‘1’ whenever the control information changes state. These bits are reset to ‘0’ whenever the DTE reads the MSR register. If the modem status interrupt is enabled (IER3), the modem generates an interrupt on the ∝P HINT pin whenever MSR bits 3:0 are set to ‘1.’

Bit 7

Data Carrier Detect (DCD)—When this bit is set to ‘1’, it indicates that the remote modem data carrier has been detected

(refer to the &C command).

 

 

 

Bit 6

Ring Indicate (RI)—This bit indicates when a ring signal has been detected.

 

 

 

Data Set Ready (DSR)—This bit indicates when the modem is ready to establish a communication link.

Bit 5

When entering voice mode, DSR is set to 1. DSR is used for voice playback/record DMA mode to indicate when the DTE

has not responded to a modem DMA data transfer request. DSR is set to 1 when DMA data are being transferred; DSR is

 

set to 0 when a new DMA transfer has not occurred with 1.7 ms after the previous DMA transfer. DSR works similarly to a

 

DMA terminal count.

 

 

Bit 4

Clear To Send (CTS)—When this bit is set to ‘1’, it indicates to the DTE that the modem is ready to receive data.

 

 

Bit 3

Delta Data Carrier Detect (DDCDD)—When this bit is set to ‘1’, it indicates that the DCD bit has changed its value since

the DTE last read the MSR register.

 

 

 

Bit 2

Trailing Edge of Ring Indicator (TERI)—This bit is set to ‘1’ after the RI signal goes from a high to low state.

 

 

Bit 1

Delta Data Set Ready (DDSR)—When this bit is set to ‘1’, it indicates that the DSR bit has changed its value since the

DTE last read the MSR register.

 

 

 

Bit 0

Delta Clear to Send (DCTS)—When this bit is set to ‘1’, it indicates that the CTS bit has changed its value since the DTE

last read the MSR register.

 

 

 

536EX Chipset Developer’s Manual

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Intel Confidential

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Contents January 536EX ChipsetDeveloper’s Manual 536EX Chipset Developer’s Manual Intel ConfidentialContents ContentsFigures Tables Description Revision HistoryDate Revision1.1Controllerless Modem Driver Overview IntroductionKernel - ring0 Figure 1. WDM Driver Block Diagram1.1.2Windows 95 and Windows User applications1.2V.90/V.92 and V.34 Data Modes Figure 2. VxD Mini Port Driver Block Diagram1.3Modem Connection Overview Table 3. DCE-to-ISPData Rates for V.90 Mode Table 1. DTE-to-DCEData Rates for Each ModeTable 2. DCE-to-DCEData Rates for Each Mode Table 4. DTE-ModemData Rate Response Codes 1.4.1Sending Commands1.4.3Dial Modifier 1.4.2AT Escape SequencesTable 5. Data Mode Command Summary AT Command Summary TablesAT Command Summary Tables Table 5. Data Mode Command Summary Continued Result code type 536EX Chipset Developer’s Manual Generate data mode calling tone Table 6. V.44/V.42/V.42 bis MNP Command Summary 536EX Chipset Developer’s Manual Table 8. Fax Class 1 Command Summary Table 7. Fax Identity Command SummaryTable 10. Voice DTE→DCE Character Pairs Table 9. IS-101Voice Command SummaryTable 11. Voice DTE←DCE Character Pairs Table 10. Voice DTE→DCE Character Pairs ContinuedTable 13. S-RegisterSummary Table 11. Voice DTE←DCE Character Pairs ContinuedTable 12. Dial Modifiers Table 13. S-RegisterSummary Continued Data Mode AT COMMANDS Data Mode AT COMMANDS•ATW2 Table 14. Data Reporting Wn MappingFigure 3. Example of a Remote Connection ATW0Examples +FMFR?, +FMDL?, +FREV? 3.8Modem-to-ModemConnection Data Rates 3.6Online Command Mode Escape Codes, On3.7Hanging Up Hn, S10, Zn, &D2 536EX Chipset Developer’s Manual +++AT +PMH=0+PCW=0 +VCID=1536EX Chipset Developer’s Manual hook to connect the call. Now you can answer the phone and talk. After completing your voice conversation, the modem will issue another +PMHF and ATO command to initiate a Quick Connect. If the server rejects the request to go on hold, the user can stay on line ATO command issued or disconnect from his initial data connection ATH command issued Table 16. Supported Modulation Types 3.9.1Local Analog Loopback AT&T1 3.9Diagnostic Testing S18, &TnLocal Modem or Test Modem 3.9.2Local Analog Loopback With Self-TestAT&T8LOCAL MODEM Figure 6. Local Analog Loopback TestLicensing Requirements for Hayes Escape Sequence 3.10.1Time-IndependentEscape Sequencechar1 = char2 = char3 = escape character S2 <char1><char2><char3><AT command><contents of S3>Format 3.10.2Hayes* Escape Sequence Table 18. Data Mode Command Descriptions536EX Chipset Developer’s Manual Sn=x 536EX Chipset Developer’s Manual Data Mode AT COMMANDSIntel Confidential 536EX Chipset Developer’s Manual AT&V0 536EX Chipset Developer’s Manual Definition Command DefaultIndication 1, 0, 536EX Chipset Developer’s Manual 1, 1, +ESR+ETBM +ILRR=m +GMR+GSN +IFC536EX Chipset Developer’s Manual see ‘m’ <carrier>Description +MS=m+PMHR +PHSW=+PMHF <value>536EX Chipset Developer’s Manual Table 19. Operating Modes Error Correction and Data Compression4Error Correction and Data Compression NOTES Table 20. Resulting +ES Connection Types536EX Chipset Developer’s Manual Error Correction and Data CompressionIntel Confidential 536EX Chipset Developer’s Manual <max string> +DR=mdirection +DS=m+EFCS=m 3768+ER=m +ES=m Fax Class 1 AT Commands Fax Class 1 AT Commands5.1Fax Identity Commands 5.2Fax Class 1 CommandsTable 23. <mod> Selection Table Figure 8. T.30 HDLC Frame Format Table 24. Fax Mode Command Descriptions shown in Table 23 on page Table 24. Fax Mode Command Descriptions Continued+FRH=m Refer to Table 23 on page+FTH=m IS-101Voice Mode AT Commands IS-101Voice Mode AT Commands6.2Relay Control Table 25. Voice Mode Command Descriptions6.1DTMF Detection Reporting m = <deassert>, <assert> +FLO=m+VDR=m m=<enable>, <report>+VEM=m m = <mask>Intel Confidential +VIP +VLS=m Preassigned Voice I/O LabelsRelay/Playback Control: cont Voice I/O Primitive Codes+VSD=m +VRXm = <sds>, <sdi> Transmission: Range: m= <cml>, <vsr>, <scs>, <sel>+VSM=m +VSP=m Compression Method Selection: contfactory default is ‘0’ none +VTS=mDTMF and Tone Generation: cont CommandDefault DescriptionS-Registers S-RegistersTable 26. S-RegisterCommand Descriptions 536EX Chipset Developer’s Manual Intel ConfidentialS-Registers 536EX Chipset Developer’s Manual Intel ConfidentialS-Registers 536EX Chipset Developer’s Manual Intel ConfidentialS-Registers 536EX Chipset Developer’s Manual Table 27. Caller ID Tags for Formatted Reporting Caller IDCaller ID NMBR = RING DATE = TIME = NMBR = NAME = DOE JOHN MESG =RING RING <DLE> RFigure 11. UART Emulation in Intelsdb.VxD Parallel Host Interface 16C450/16C550AUART Parallel Host Interface 16C450/16C550A UARTUART Receiver Flow Diagram UART Transmitter Flow DiagramNAME REGISTERBIT NUMBER ADDRESSFigure 15. Modem Status Register MSR 9.2.1Scratch Register SCR9.2.2Modem Status Register MSR Figure 14. Scratch Register SCRFigure 16. Line Status Register LSR 9.2.3Line Status Register LSRFigure 18. Line Control Register LCR 9.2.4Modem Control Register MCR9.2.5Line Control Register LCR Figure 17. Modem Control Register MCRFigure 19. FIFO Control Register FCR 9.2.6FIFO Control Register FCRRegister Table 28. Interrupt Control Functions 9.2.7Interrupt Identity Register IIRFigure 20. Interrupt Identity Register IIR Figure 22. Transmitter Holding Register THR 9.2.8Interrupt Enable Register IERFigure 21. Interrupt Enable Register IER 9.2.9Transmitter Holding Register THRFigure 24. Divisor Latch Registers DLM and DLL 9.2.10Receiver Buffer Register RBR9.2.11Divisor Latch Registers DLM and DLL Figure 23. Receiver Buffer Register RBR9.3.2FIFO Polled Mode Operation 9.316C550A UART FIFO Operation9.3.1FIFO Interrupt Mode Operation 536EX Chipset Developer’s Manual Intel ConfidentialParallel Host Interface 16C450/16C550A UART
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