Intel 536EX manual 9.2.8Interrupt Enable Register IER, 9.2.9Transmitter Holding Register THR

Page 100
9.2.8Interrupt Enable Register (IER)

Parallel Host Interface 16C450/16C550A UART

Bit 3

Interrupt ID Bit 2—In 16C450 mode, this bit is always a ‘0’.

In FIFO mode, both this bit and bit IIR2 are set whenever a time-out interrupt is pending.

 

 

 

Bits 2:1

Interrupt ID Bits ID0 and ID1—These two bits are used to identify the highest-priority interrupt as shown in Table 28.

 

 

 

Interrupt Pending—This bit indicates when a modem interrupt is pending. Whenever this bit is equal to ‘0’, then one

Bit 0

or more interrupts are pending. Whenever this bit is equal to ‘1’, then no interrupts are pending. When an interrupt has

occurred, the host can determine the cause of the interrupt by looking at the IIR interrupt ID bits 0 and 1 (and interrupt

 

 

ID bit 2 for FIFO mode).

 

 

9.2.8Interrupt Enable Register (IER)

Figure 21. Interrupt Enable Register (IER)

Register 1

(DLAB = 0)

0

0

0

0

MSIE

RLSIE

THREIE

RDAIE

 

This register is used to enable up to five types of UART interrupts: receiver line status, received

 

data available, character time-out indication (FIFO mode only), Transmitter Holding register

 

empty, and modem status. Each enabled interrupt can individually cause an interrupt to host on the

 

∝P HINT output pin. To cause an interrupt to the host (HINT), both the interrupt enable bit and

 

OUT2 (MCR2) must be set to ‘1’.

 

 

Bits 7:4

Not used—These bits are permanently set to ‘0’.

 

 

Bit 3

MSIE (Modem Status Interrupt Enabled)—when set to ‘1’, this bit enables the modem status interrupt.

 

 

Bit 2

RLSIE (Receiver Line Status Interrupt Enabled)—when set to ‘1’, this bit enables the receiver line status interrupt.

 

 

Bit 1

THREIE (Transmitter Holding Register Empty Interrupt Enabled)—when set to ‘1’, this bit enables the Transmitter

Holding register empty interrupt.

 

 

 

Bit 0

RDAIE (Received Data Available Interrupt Enabled)—when set to ‘1’, this bit enables the received data available

interrupt.

 

 

 

9.2.9Transmitter Holding Register (THR)

Figure 22. Transmitter Holding Register (THR)

Register 0

(DLAB = 0)

THR

The THR (Transmitter Holding register) is a write-only register used for sending data and AT commands to the modem.

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536EX Chipset Developer’s Manual

Intel Confidential

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Contents Developer’s Manual 536EX ChipsetJanuary Intel Confidential 536EX Chipset Developer’s ManualContents ContentsFigures Tables Revision History DateRevision DescriptionIntroduction 1.1Controllerless Modem Driver OverviewFigure 1. WDM Driver Block Diagram 1.1.2Windows 95 and WindowsUser applications Kernel - ring0Figure 2. VxD Mini Port Driver Block Diagram 1.2V.90/V.92 and V.34 Data Modes1.3Modem Connection Overview Table 2. DCE-to-DCEData Rates for Each Mode Table 1. DTE-to-DCEData Rates for Each ModeTable 3. DCE-to-ISPData Rates for V.90 Mode 1.4.1Sending Commands Table 4. DTE-ModemData Rate Response Codes1.4.2AT Escape Sequences 1.4.3Dial ModifierAT Command Summary Tables AT Command Summary TablesTable 5. Data Mode Command Summary Table 5. Data Mode Command Summary Continued Result code type AT Command Summary Tables Generate data mode calling tone Table 6. V.44/V.42/V.42 bis MNP Command Summary AT Command Summary Tables Table 7. Fax Identity Command Summary Table 8. Fax Class 1 Command SummaryTable 9. IS-101Voice Command Summary Table 10. Voice DTE→DCE Character PairsTable 10. Voice DTE→DCE Character Pairs Continued Table 11. Voice DTE←DCE Character PairsTable 12. Dial Modifiers Table 11. Voice DTE←DCE Character Pairs ContinuedTable 13. S-RegisterSummary Table 13. S-RegisterSummary Continued Data Mode AT COMMANDS Data Mode AT COMMANDSTable 14. Data Reporting Wn Mapping Figure 3. Example of a Remote ConnectionATW0 •ATW2Intel Confidential +FMFR?, +FMDL?, +FREV? 3.7Hanging Up Hn, S10, Zn, &D2 3.6Online Command Mode Escape Codes, On3.8Modem-to-ModemConnection Data Rates Intel Confidential +PMH=0 +PCW=0+VCID=1 +++ATIntel Confidential hook to connect the call. Now you can answer the phone and talk. After completing your voice conversation, the modem will issue another +PMHF and ATO command to initiate a Quick Connect. If the server rejects the request to go on hold, the user can stay on line ATO command issued or disconnect from his initial data connection ATH command issued Table 16. Supported Modulation Types 3.9Diagnostic Testing S18, &Tn 3.9.1Local Analog Loopback AT&T13.9.2Local Analog Loopback With Self-TestAT&T8 LOCAL MODEMFigure 6. Local Analog Loopback Test Local Modem or Test Modem3.10.1Time-IndependentEscape Sequence Licensing Requirements for Hayes Escape SequenceFormat <char1><char2><char3><AT command><contents of S3>char1 = char2 = char3 = escape character S2 Table 18. Data Mode Command Descriptions 3.10.2Hayes* Escape SequenceIntel Confidential Sn=x Intel Confidential Data Mode AT COMMANDS536EX Chipset Developer’s Manual Data Mode AT COMMANDS AT&V0 Intel Confidential Indication Command DefaultDefinition 1, 0, Intel Confidential +ETBM +ESR1, 1, +GMR +GSN+IFC +ILRR=mData Mode AT COMMANDS <carrier> Description+MS=m see ‘m’+PHSW= +PMHF<value> +PMHRIntel Confidential Error Correction and Data Compression Error Correction and Data Compression4Table 19. Operating Modes Table 20. Resulting +ES Connection Types NOTESIntel Confidential Error Correction and Data Compression536EX Chipset Developer’s Manual Intel Confidential +DR=m direction+DS=m <max string>3768 +EFCS=m+ER=m +ES=m Fax Class 1 AT Commands 5.1Fax Identity Commands5.2Fax Class 1 Commands Fax Class 1 AT CommandsTable 23. <mod> Selection Table Figure 8. T.30 HDLC Frame Format Table 24. Fax Mode Command Descriptions Table 24. Fax Mode Command Descriptions Continued +FRH=mRefer to Table 23 on page shown in Table 23 on page+FTH=m IS-101Voice Mode AT Commands IS-101Voice Mode AT Commands6.1DTMF Detection Reporting Table 25. Voice Mode Command Descriptions6.2Relay Control +FLO=m m = <deassert>, <assert>m=<enable>, <report> +VDR=mm = <mask> +VEM=mIntel Confidential +VIP Preassigned Voice I/O Labels +VLS=mVoice I/O Primitive Codes Relay/Playback Control: contm = <sds>, <sdi> +VRX+VSD=m +VSM=m m= <cml>, <vsr>, <scs>, <sel>Transmission: Range: Compression Method Selection: cont +VSP=mfactory default is ‘0’ +VTS=m noneCommand DefaultDescription DTMF and Tone Generation: contTable 26. S-RegisterCommand Descriptions S-RegistersS-Registers S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Caller ID Caller IDTable 27. Caller ID Tags for Formatted Reporting RING DATE = TIME = NMBR = NAME = DOE JOHN MESG = RING RING<DLE> R NMBR =Parallel Host Interface 16C450/16C550A UARTParallel Host Interface 16C450/16C550A UART Figure 11. UART Emulation in Intelsdb.VxDUART Transmitter Flow Diagram UART Receiver Flow DiagramREGISTER BIT NUMBERADDRESS NAME9.2.1Scratch Register SCR 9.2.2Modem Status Register MSRFigure 14. Scratch Register SCR Figure 15. Modem Status Register MSR9.2.3Line Status Register LSR Figure 16. Line Status Register LSR9.2.4Modem Control Register MCR 9.2.5Line Control Register LCRFigure 17. Modem Control Register MCR Figure 18. Line Control Register LCRRegister 9.2.6FIFO Control Register FCRFigure 19. FIFO Control Register FCR Figure 20. Interrupt Identity Register IIR 9.2.7Interrupt Identity Register IIRTable 28. Interrupt Control Functions 9.2.8Interrupt Enable Register IER Figure 21. Interrupt Enable Register IER9.2.9Transmitter Holding Register THR Figure 22. Transmitter Holding Register THR9.2.10Receiver Buffer Register RBR 9.2.11Divisor Latch Registers DLM and DLLFigure 23. Receiver Buffer Register RBR Figure 24. Divisor Latch Registers DLM and DLL9.3.1FIFO Interrupt Mode Operation 9.316C550A UART FIFO Operation9.3.2FIFO Polled Mode Operation Parallel Host Interface 16C450/16C550A UART Intel Confidential536EX Chipset Developer’s Manual
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