Intel 536EX 9.2.7Interrupt Identity Register IIR, Intel Confidential, Interrupt Control Functions

Parallel Host Interface 16C450/16C550A UART

9.2.7Interrupt Identity Register (IIR)

b

Figure 20. Interrupt Identity Register (IIR)

Register 2

(read-only)

FIFO EN FIFO EN

0

VDMA

Int. ID 2

Int. ID 1 Int. ID 0 Int. Pen.

This read-only register indicates when the transmitter and receiver FIFOs are enabled, and the source of highest-priority pending interrupt to the DTE. Five levels of modem interrupt sources in order of priority are: receiver line status, received data ready, character time-out indication, transmitter holding register empty, and modem status. When the DTE reads the IIR, the modem freezes all interrupts and indicates the highest-priority pending interrupt. While the DTE is reading the IIR register, the modem records new interrupts but does not change its current indication until the read process is completed.

Table 28. Interrupt Control Functions

FIFO			Interrupt
Mode		Identification					Interrupt Source and Reset Functions
Only			Register
Bit 3	Bit 2			Bit 1	Bit 0	Priority
					Int.		Interrupt Type	Interrupt Source	Interrupt Reset Control
						Level
ID 2		ID1		ID0	Pend.
0	0			0	1	–	None	None	–
							Receiver Line	Overrun Error, Parity Error,	Reading the LSR (Line
0	1			1	0	Highest		Framing Error or Break
							Status		Status register)
								Interrupt
									Reading the RBR (Receiver
0	1			0	0	Second	Received Data	Receiver Data Available or	Buffer register) or the FIFO
							Available	Trigger Level Reached	Drops below the Trigger
									Level
								No characters have been
							Character	removed from or entered
								into the RCVR FIFO during	Reading the RBR (Receiver
1	1			0	0	Second	Time-out	the last four character times,
									Buffer register)
							Indication	and there is at least one
								character in it during this
								time
							Transmitter		Reading the IIR register (if
							Holding	Transmitter Holding
0	0			1	0	Third			the source of interrupt) or
							Register	Register Empty	writing into the Transmitter
							Empty		Holding register
								Clear to Send,
0	0			0	0	Fourth	Modem Status	Data Set Ready,	Reading the MSR (Modem
								Ring Indicator, or Data	Status register)
								Carrier Detect
Bits 7:6		FIFOs Enable Bits—These two bits are set whenever FCR0 = 1.
Bits 5		Not used—This bit is permanently set to ‘0’.
Bit 4		Reserved

536EX Chipset Developer’s Manual 99

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