Intel 536EX Intel Confidential, AT Command Summary Tables, V.44/V.42/V.42 bis MNP Command Summary

Page 19
Table 6. V.44/V.42/V.42 bis MNP Command Summary

AT Command Summary Tables

a.For Data mode, the factory default setting is AT+MS=V92, 1, 0, 0, 0, 0 to send at speeds of 33,600 bps or below and receive at speeds of 53,333 bps and below.

Note: See the relevant sections in the 536EX Developer’s Manual for full command description and parameter ranges.

Table 6. V.44/V.42/V.42 bis MNP Command Summary

Note

Command

Function

 

 

Default

Range

Reported

 

 

by &Vn

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*

%An

Set auto-reliable fallback character

13

0–127

yes

 

 

 

 

 

 

 

*

%Cn

MNP 5 data compression control

1

0, 1

yes

 

 

 

 

 

 

 

 

 

%C0

No compression

 

 

 

 

 

 

 

 

 

 

 

 

%C1

Enables MNP5 data compression

 

 

 

 

 

 

 

 

 

 

 

*

\An

MNP block size

 

3

0–3

yes

 

 

 

 

 

 

 

 

 

\A0

Maximum 64 characters

 

 

 

 

 

 

 

 

 

 

 

 

 

\A1

Maximum 128 characters

 

 

 

 

 

 

 

 

 

 

 

 

 

\A2

Maximum 192 characters

 

 

 

 

 

 

 

 

 

 

 

 

 

\A3

Maximum 256 characters

 

 

 

 

 

 

 

 

 

 

 

 

 

\Bn

Set transmit break

 

3

0–9

 

 

 

 

 

 

 

 

 

*

\Cn

Set auto-reliable buffer

 

0

0–2

yes

 

 

 

 

 

 

 

 

 

\C0

No data buffering

 

 

 

 

 

 

 

 

 

 

 

 

\C1

Four-second buffer until 200 characters in the buffer or

 

 

 

 

detection of a SYN character

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

\C2

No buffering. Connects non-V.42 modems to V.42

 

 

 

 

modem

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*

\Gn

Set modem port flow control

 

0

0, 1

yes

 

 

 

 

 

 

 

 

 

\G0

Disables port flow control

 

 

 

 

 

 

 

 

 

 

 

 

\G1

Sets port flow control to XON/XOFF

 

 

 

 

 

 

 

 

 

 

 

*

\Jn

bps rate adjust control

 

0

0, 1

yes

 

 

 

 

 

 

 

 

 

\J0

Disables rate adjust

 

 

 

 

 

 

 

 

 

 

 

 

 

\J1

Enables rate adjust

 

 

 

 

 

 

 

 

 

 

 

 

 

\Kn

Set break control

 

5

0–5

no

 

 

 

 

 

 

 

 

 

 

 

 

connect state, transmits

 

Enters command mode,

 

 

 

 

 

 

 

no break sent

 

 

 

 

 

 

 

 

 

 

 

 

\K0

 

 

 

 

 

 

 

 

 

command state, transmits

 

Destructive/expedited

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connect state, receives

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connect state, transmits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

\K1

command state, transmits

Destructive/expedited

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

connect state, receives

 

 

 

 

 

 

 

 

 

 

 

 

 

 

* Value saved in NVRAM.

536EX Chipset Developer’s Manual

19

Intel Confidential

Image 19
Contents Developer’s Manual 536EX ChipsetJanuary 536EX Chipset Developer’s Manual Intel ConfidentialContents ContentsFigures Tables Description Revision HistoryDate Revision1.1Controllerless Modem Driver Overview IntroductionKernel - ring0 Figure 1. WDM Driver Block Diagram1.1.2Windows 95 and Windows User applications1.2V.90/V.92 and V.34 Data Modes Figure 2. VxD Mini Port Driver Block Diagram1.3Modem Connection Overview Table 2. DCE-to-DCEData Rates for Each Mode Table 1. DTE-to-DCEData Rates for Each ModeTable 3. DCE-to-ISPData Rates for V.90 Mode Table 4. DTE-ModemData Rate Response Codes 1.4.1Sending Commands1.4.3Dial Modifier 1.4.2AT Escape SequencesAT Command Summary Tables AT Command Summary TablesTable 5. Data Mode Command Summary Table 5. Data Mode Command Summary Continued Result code type 536EX Chipset Developer’s Manual Generate data mode calling tone Table 6. V.44/V.42/V.42 bis MNP Command Summary 536EX Chipset Developer’s Manual Table 8. Fax Class 1 Command Summary Table 7. Fax Identity Command SummaryTable 10. Voice DTE→DCE Character Pairs Table 9. IS-101Voice Command SummaryTable 11. Voice DTE←DCE Character Pairs Table 10. Voice DTE→DCE Character Pairs ContinuedTable 12. Dial Modifiers Table 11. Voice DTE←DCE Character Pairs ContinuedTable 13. S-RegisterSummary Table 13. S-RegisterSummary Continued Data Mode AT COMMANDS Data Mode AT COMMANDS•ATW2 Table 14. Data Reporting Wn MappingFigure 3. Example of a Remote Connection ATW0Intel Confidential +FMFR?, +FMDL?, +FREV? 3.7Hanging Up Hn, S10, Zn, &D2 3.6Online Command Mode Escape Codes, On3.8Modem-to-ModemConnection Data Rates Intel Confidential +++AT +PMH=0+PCW=0 +VCID=1Intel Confidential hook to connect the call. Now you can answer the phone and talk. After completing your voice conversation, the modem will issue another +PMHF and ATO command to initiate a Quick Connect. If the server rejects the request to go on hold, the user can stay on line ATO command issued or disconnect from his initial data connection ATH command issued Table 16. Supported Modulation Types 3.9.1Local Analog Loopback AT&T1 3.9Diagnostic Testing S18, &TnLocal Modem or Test Modem 3.9.2Local Analog Loopback With Self-TestAT&T8LOCAL MODEM Figure 6. Local Analog Loopback TestLicensing Requirements for Hayes Escape Sequence 3.10.1Time-IndependentEscape SequenceFormat <char1><char2><char3><AT command><contents of S3>char1 = char2 = char3 = escape character S2 3.10.2Hayes* Escape Sequence Table 18. Data Mode Command DescriptionsIntel Confidential Sn=x Intel Confidential Data Mode AT COMMANDS536EX Chipset Developer’s Manual 536EX Chipset Developer’s Manual AT&V0 Intel Confidential Indication Command DefaultDefinition 1, 0, Intel Confidential +ETBM +ESR1, 1, +ILRR=m +GMR+GSN +IFC536EX Chipset Developer’s Manual see ‘m’ <carrier>Description +MS=m+PMHR +PHSW=+PMHF <value>Intel Confidential Error Correction and Data Compression Error Correction and Data Compression4Table 19. Operating Modes NOTES Table 20. Resulting +ES Connection TypesIntel Confidential Error Correction and Data Compression536EX Chipset Developer’s Manual Intel Confidential <max string> +DR=mdirection +DS=m+EFCS=m 3768+ER=m +ES=m Fax Class 1 AT Commands Fax Class 1 AT Commands5.1Fax Identity Commands 5.2Fax Class 1 CommandsTable 23. <mod> Selection Table Figure 8. T.30 HDLC Frame Format Table 24. Fax Mode Command Descriptions shown in Table 23 on page Table 24. Fax Mode Command Descriptions Continued+FRH=m Refer to Table 23 on page+FTH=m IS-101Voice Mode AT Commands IS-101Voice Mode AT Commands6.1DTMF Detection Reporting Table 25. Voice Mode Command Descriptions6.2Relay Control m = <deassert>, <assert> +FLO=m+VDR=m m=<enable>, <report>+VEM=m m = <mask>Intel Confidential +VIP +VLS=m Preassigned Voice I/O LabelsRelay/Playback Control: cont Voice I/O Primitive Codesm = <sds>, <sdi> +VRX+VSD=m +VSM=m m= <cml>, <vsr>, <scs>, <sel>Transmission: Range: +VSP=m Compression Method Selection: contfactory default is ‘0’ none +VTS=mDTMF and Tone Generation: cont CommandDefault DescriptionTable 26. S-RegisterCommand Descriptions S-RegistersS-Registers S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Intel Confidential536EX Chipset Developer’s Manual S-Registers Caller ID Caller IDTable 27. Caller ID Tags for Formatted Reporting NMBR = RING DATE = TIME = NMBR = NAME = DOE JOHN MESG =RING RING <DLE> RFigure 11. UART Emulation in Intelsdb.VxD Parallel Host Interface 16C450/16C550AUART Parallel Host Interface 16C450/16C550A UARTUART Receiver Flow Diagram UART Transmitter Flow DiagramNAME REGISTERBIT NUMBER ADDRESSFigure 15. Modem Status Register MSR 9.2.1Scratch Register SCR9.2.2Modem Status Register MSR Figure 14. Scratch Register SCRFigure 16. Line Status Register LSR 9.2.3Line Status Register LSRFigure 18. Line Control Register LCR 9.2.4Modem Control Register MCR9.2.5Line Control Register LCR Figure 17. Modem Control Register MCRRegister 9.2.6FIFO Control Register FCRFigure 19. FIFO Control Register FCR Figure 20. Interrupt Identity Register IIR 9.2.7Interrupt Identity Register IIRTable 28. Interrupt Control Functions Figure 22. Transmitter Holding Register THR 9.2.8Interrupt Enable Register IERFigure 21. Interrupt Enable Register IER 9.2.9Transmitter Holding Register THRFigure 24. Divisor Latch Registers DLM and DLL 9.2.10Receiver Buffer Register RBR9.2.11Divisor Latch Registers DLM and DLL Figure 23. Receiver Buffer Register RBR9.3.1FIFO Interrupt Mode Operation 9.316C550A UART FIFO Operation9.3.2FIFO Polled Mode Operation Parallel Host Interface 16C450/16C550A UART Intel Confidential536EX Chipset Developer’s Manual