Intel 915GME user manual Isi

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Mobile Intel® 915GME Express Chipset —About This Manual

 

 

 

needed to ensure the setup time of the receiver. More precisely,

 

 

 

flight time is defined as:

 

 

 

The time difference between a signal at the input pin of a

 

 

 

 

receiving agent crossing the switching voltage (adjusted to

 

 

 

 

meet the receiver manufacturer’s conditions required for

 

 

 

 

AC timing specifications; i.e., ringback, etc.) and the output

 

 

 

 

pin of the driving agent crossing the switching voltage

 

 

 

 

when the driver is driving a test load used to specify the

 

 

 

 

driver’s AC timings.

 

 

 

Maximum and Minimum Flight Time - Flight time variations

 

 

 

 

are caused by many different parameters. The more

 

 

 

 

obvious causes include variation of the board dielectric

 

 

 

 

constant, changes in load condition, crosstalk, power noise,

 

 

 

 

variation in termination resistance, and differences in I/O

 

 

 

 

buffer performance as a function of temperature, voltage,

 

 

 

 

and manufacturing process. Some less obvious causes

 

 

 

 

include effects of Simultaneous Switching Output (SSO)

 

 

 

 

and packaging effects.

 

 

 

Maximum flight time is the largest acceptable flight time a

 

 

 

 

network will experience under all conditions.

 

 

 

Minimum flight time is the smallest acceptable flight time a

 

 

 

 

network will experience under all conditions.

 

 

IrDA

IrDA is an acronym for Infrared Data Association, and this

 

 

 

association has outlined a specification for serial communication

 

 

 

between two devices via a bi-directional infrared data port. The

 

 

 

915GM platform has such a port and it is located on the rear of

 

 

 

the platform between the two USB connectors.

 

 

ISI

Inter-symbol interference is the effect of a previous signal (or

 

 

 

transition) on the interconnect delay. For example, when a

 

 

 

signal is transmitted down a line and the reflections due to the

 

 

 

transition have not completely dissipated, the following data

 

 

 

transition launched onto the bus is affected. ISI is dependent

 

 

 

upon frequency, time delay of the line, and the reflection

 

 

 

coefficient at the driver and receiver. ISI may impact both timing

 

 

 

and signal integrity.

 

 

Network

The network is the trace of a Printed Circuit Board (PCB) that

 

 

 

completes an electrical connection between two or more

 

 

 

components.

 

 

Overshoot

The maximum voltage observed for a signal at the device pad,

 

 

 

measured with respect to VCC.

 

 

Pad

The electrical contact point of a semiconductor die to the

 

 

 

package substrate. A pad is only observable in simulations.

 

 

Pin

The contact point of a component package to the traces on a

 

 

 

substrate, such as the motherboard. Signal quality and timings

 

 

 

may be measured at the pin.

 

 

Power-Good

“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high

 

 

 

signal) indicates that all of the system power supplies and clocks

 

 

 

are stable. PWRGOOD should go active a predetermined time

 

 

 

after system voltages are stable and should go inactive as soon

 

 

 

as any of these voltages fail their specifications.

 

 

Ringback

The voltage to which a signal changes after reaching its

 

 

 

maximum absolute value. Ringback may be caused by

 

 

 

reflections, driver oscillations, or other transmission line

 

 

 

phenomena.

Mobile Intel® 915GME Express Chipset

 

 

Development Kit User’s Manual

 

April 2007

10

 

 

 

Order Number: 317230-001US

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Contents Mobile Intel 915GME Express Chipset Development Kit User’s ManualOrder Number 317230-001US Contents Clock Generation Figures TablesRevision History Content Overview Text ConventionsMicrofarads Glossary of Terms and Acronyms ADD2ISI Acronyms Sheet 1 Acronym DefinitionElectronic Support Systems Support OptionsProduct Literature Additional Technical SupportRelated Documents Related DocumentsDocument Title Order Number Mobile Intel 915GME Express Chipset Features OverviewClocking 1 AMI* Bios Software Key FeaturesIncluded Hardware and Documentation Before You Begin Setting Up the Evaluation Board Remove any hardware unless the system is unpluggedConfiguring the Bios Block Diagram Theory of OperationMobile Intel 915GME Express Chipset Block Diagram Mechanical Form FactorMobile Intel 915GME Express Chipset System Features and OperationThermal Management System MemoryAdvanced Graphics and Display Interface 2 ICH6-M1.2 DMI PCI Express Slots2.4 AC’97 and High Definition Audio USB ConnectorsOn-Board LAN ATA / StorageSerial, IrDA Bios Firmware Hub FWHLPC Super I/O SIO/LPC Slot System Management Controller SMC/Keyboard ControllerSystem I/O and Connector Summary Sata Support VGA ConnectorPCI Express Support IDE SupportClock Generation Power Management StatesPost Code Debugger Transition to S4 Mobile Intel 915GME Express Chipset Power Management StatesTransition to S1 or S3 Transition to S5Mobile Intel 915GME Express Chipset Voltage Rails Sheet 1 Power Measurement SupportVoltage Groups Voltage Rail Reference Designator Mobile Intel 915GME Express Chipset Voltage Rails Sheet 2 Mobile Intel 915GME Express Chipset Voltage Rails Sheet 3 Mobile Intel 915GME Express Chipset Voltage Rails Sheet 4 Primary Features Hardware ReferenceVID Leds FWHSMC/KBC Smsc SIOBack Panel Connectors Configuration Settings SW9J2 Supported Configuration Jumper/Switch SettingsDefault Setting Optional Setting Option Setting Desig SW4A1Unsupported Jumper Default Position Jumper PinsPower On and Reset Buttons 1 H8 Programming Headers LEDsOther Headers Mobile Intel 915GME Express Chipset LED Function LegendH8 Programming Jumpers Expansion Slots and Sockets2.1 478 Pin Grid Array Micro-FCPGA Socket Expansion Slots and SocketsPCI Express Pin DescriptionPRSNT2# PRSNT#2ADD2 Slot J6C1 Sheet 1 2.3 ADD2 SlotPCI Express x16 Pinout J6C1 Sheet 3 Pin NumberADD2 Slot J6C1 Sheet 2 ADD2 Slot J6C1 Sheet 3 PCI Express x1 Pinout J7C2, J8C1 & J8D1 GND Jtag TCK Smclk Jtag TDI Smdat Jtag TDO Jtag TMSPin Signal IDE ConnectorIDE Connector J7J2 Sata PinoutSata Port 0 Mobile Drive Connector Pinout J8J3 Fan ConnectorsSata Port 2 Power Connector Pinout J6H3 Fan Connectors J3F4 and J3B1Appendix a Heat Sink Installation Instructions Back Plate Pins CPU Fan Header