Intel 915GME user manual Glossary of Terms and Acronyms, ADD2

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About This Manual—Mobile Intel® 915GME Express Chipset

1.3Glossary of Terms and Acronyms

This section defines conventions and terminology used throughout this document.

ADD2

ADD2 is an acronym for Advanced Digital Display, 2nd

 

Generation. ADD2 video interfaces come in two configurations:

 

Normal and Reversed. The normal is often referred to as ADD2

 

or ADD2-N and the reversed is referred to as ADD2-R. The

 

915GM platform can only support the ADD2-R video interface.

Aggressor

A network that transmits a coupled signal to another network.

AGTL+

The front-side bus uses a bus technology called AGTL+, or

 

Assisted Gunning Transceiver Logic. AGTL+ buffers are open-

 

drain, and require pull-up resistors to provide the high logic level

 

and termination. AGTL+ output buffers differ from GTL+ buffers

 

with the addition of an active pMOS pull-up transistor to assist

 

the pull-up resistors during the first clock of a low-to-high

 

voltage transition.

Asynchronous GTL+ The processor does not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/ NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output signals (FERR# and IERR#) and non- AGTL+ signals (THERMTRIP# and PROCHOT#) also utilize GTL+ output buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation to BCLK[1:0], and are therefore referred to as “Asynchronous GTL+ Signals”. However, all of the Asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them.

Bus Agent

A component or group of components that, when combined,

 

represent a single load on the AGTL+ bus.

Crosstalk

The reception on a victim network of a signal imposed by

 

aggressor network(s) through inductive and capacitive coupling

 

between the networks.

 

Backward Crosstalk - Coupling that creates a signal in a

 

 

victim network that travels in the opposite direction as the

 

 

aggressor’s signal.

 

Forward Crosstalk - Coupling that creates a signal in a

 

 

victim network that travels in the same direction as the

 

 

aggressor’s signal.

 

Even Mode Crosstalk - Coupling from a signal or multiple

 

 

aggressors when all the aggressors switch in the same

 

 

direction that the victim is switching.

 

Odd Mode Crosstalk - Coupling from a signal or multiple

 

 

aggressors when all the aggressors switch in the opposite

 

 

direction that the victim is switching.

Flight Time

Flight time is a term in the timing equation that includes the

 

signal propagation delay, any effects the system has on the TCO

 

of the driver, plus any adjustments to the signal at the receiver

 

Mobile Intel® 915GME Express Chipset

April 2007

Development Kit User’s Manual

Order Number: 317230-001US

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Contents Development Kit User’s Manual Mobile Intel 915GME Express ChipsetOrder Number 317230-001US Contents Clock Generation Tables FiguresRevision History Text Conventions Content OverviewMicrofarads ADD2 Glossary of Terms and AcronymsISI Acronym Definition Acronyms Sheet 1Product Literature Support OptionsElectronic Support Systems Additional Technical SupportRelated Documents Related DocumentsDocument Title Order Number Overview Mobile Intel 915GME Express Chipset FeaturesClocking Software Key Features 1 AMI* BiosIncluded Hardware and Documentation Before You Begin Remove any hardware unless the system is unplugged Setting Up the Evaluation BoardConfiguring the Bios Theory of Operation Block DiagramMechanical Form Factor Mobile Intel 915GME Express Chipset Block DiagramThermal Management System Features and OperationMobile Intel 915GME Express Chipset System Memory1.2 DMI 2 ICH6-MAdvanced Graphics and Display Interface PCI Express SlotsOn-Board LAN USB Connectors2.4 AC’97 and High Definition Audio ATA / StorageLPC Super I/O SIO/LPC Slot Bios Firmware Hub FWHSerial, IrDA System Management Controller SMC/Keyboard ControllerSystem I/O and Connector Summary PCI Express Support VGA ConnectorSata Support IDE SupportPower Management States Clock GenerationPost Code Debugger Transition to S1 or S3 Mobile Intel 915GME Express Chipset Power Management StatesTransition to S4 Transition to S5Power Measurement Support Mobile Intel 915GME Express Chipset Voltage Rails Sheet 1Voltage Groups Voltage Rail Reference Designator Mobile Intel 915GME Express Chipset Voltage Rails Sheet 2 Mobile Intel 915GME Express Chipset Voltage Rails Sheet 3 Mobile Intel 915GME Express Chipset Voltage Rails Sheet 4 Hardware Reference Primary FeaturesSMC/KBC FWHVID Leds Smsc SIOBack Panel Connectors Configuration Settings Default Setting Optional Setting Option Setting Desig Supported Configuration Jumper/Switch SettingsSW9J2 SW4A1Jumper Pins Unsupported Jumper Default PositionPower On and Reset Buttons Other Headers LEDs1 H8 Programming Headers Mobile Intel 915GME Express Chipset LED Function Legend2.1 478 Pin Grid Array Micro-FCPGA Socket Expansion Slots and SocketsH8 Programming Jumpers Expansion Slots and SocketsPin Description PCI ExpressPRSNT#2 PRSNT2#PCI Express x16 Pinout J6C1 Sheet 3 2.3 ADD2 SlotADD2 Slot J6C1 Sheet 1 Pin NumberADD2 Slot J6C1 Sheet 2 ADD2 Slot J6C1 Sheet 3 GND Jtag TCK Smclk Jtag TDI Smdat Jtag TDO Jtag TMS PCI Express x1 Pinout J7C2, J8C1 & J8D1IDE Connector J7J2 IDE ConnectorPin Signal Sata PinoutSata Port 2 Power Connector Pinout J6H3 Fan ConnectorsSata Port 0 Mobile Drive Connector Pinout J8J3 Fan Connectors J3F4 and J3B1Appendix a Heat Sink Installation Instructions Back Plate Pins CPU Fan Header