Intel 82540EP manual PCI Features, MAC Specific Features, Features Benefits

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Networking Silicon — 82540EP

2.0Features of the 82540EP Gigabit Ethernet Controller

2.1PCI Features

	Features		Benefits

		• Application flexibility for LAN on Motherboard
	PCI Revision 2.3 support for 32-bit wide interface at		(LOM) or embedded solutions
	PCI Revision 2.3 support for 32-bit wide interface at	• 64-bit addressing for systems with more than 4
	33 MHz and 66 MHz	• 64-bit addressing for systems with more than 4
	33 MHz and 66 MHz		Gigabytes of physical memory
			Gigabytes of physical memory
		• Support for new PCI 2.3 interrupt status/control

	Algorithms that optimally use advanced PCI, MWI,	•	Efficient bus operations
	MRM, and MRL commands	•	Efficient bus operations
	MRM, and MRL commands

		• Enables CardBus operation (when used with
	CardBus Information Services (CIS) Pointer		external FLASH device and series termination on
			PCI bus)

	CLKRUN# Signal	•	PCI clock suspension for low power mobile design

2.2MAC Specific Features

	Features		Benefits

	Low-latency transmit and receive queues	• Network packets handled without waiting or buffer
	Low-latency transmit and receive queues		overflow.
			overflow.

	IEEE 802.3x compliant flow control support with	•	Control over the transmissions of pause frames
	software controllable pause times and threshold		through software or hardware triggering
	values	•	Frame loss reduced from receive overruns

	Caches up to 64 packet descriptors in a single burst	•	Efficient use of PCI bandwidth

	Programmable host memory receive buffers (256
	Bytes to 16 KBytes) and cache line size (16 Bytes to	•	Efficient use of PCI bandwidth
	256 Bytes)

	Wide, optimized internal data path architecture	• Low latency data handling
	Wide, optimized internal data path architecture	• Superior DMA transfer rate performance
		• Superior DMA transfer rate performance

	64 KByte configurable Transmit and Receive FIFO	•	No external FIFO memory requirements
	buffers	•	FIFO size adjustable to application

	Descriptor ring management hardware for transmit	• Simple software programming model
	and receive	• Simple software programming model
	and receive

	Optimized descriptor fetching and write-back	•	Efficient system memory and use of PCI
	mechanisms		bandwidth

	Mechanism available for reducing interrupts	• Maximizes system performance and throughput
	generated by transmit and receive operations	• Maximizes system performance and throughput
	generated by transmit and receive operations

	Support for transmission and reception of packets up	•	Enables jumbo frames
	to 16 KBytes	•	Enables jumbo frames
	to 16 KBytes

Datasheet

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Contents Revision April 82540EP Gigabit Ethernet ControllerDatasheet Date Revision 82540EP Networking Silicon Contents 82540EP Networking Silicon Introduction Acpi LED MdioTX MAC RX MACProduct Code Document ScopeReference Documents 82540EP Networking Silicon Application flexibility for LAN on Motherboard PCI FeaturesMAC Specific Features Features BenefitsHostOffloading PHY Specific FeaturesA server management processor Manageability FeaturesTechnology Features Additional Device FeaturesPCI Bus Interface Signal Type DefinitionsPCI Address, Data and Control Signals Symbol Type Name and FunctionTRDY# STS PARFRAME# STS IRDY# STSError Reporting Signals Arbitration SignalsInterrupt Signal System SignalsSMB Signals Eeprom and Serial Flash Interface SignalsPower Management Signals Impedance Compensation SignalsOther Signals Miscellaneous SignalsLED Signals XTAL2 AnalogXTAL1 Analog Supplies Test Interface SignalsPower Supply Connections Digital SuppliesCTRL15 Control SignalsGround and No Connects GNDRecommended Operating Conditions a Sheet 1 Absolute Maximum RatingsRecommended Operating Conditions Absolute Maximum RatingsaRecommended Operating Conditions a Sheet 2 DC SpecificationsDC Characteristics Power Specifications D0aPower Specifications Complete Subsystem Power Specifications D3coldPower Specifications Dr Uninitialized = V SS O CharacteristicsSymbol Parameter Condition Min Typ Max AC Characteristics Tcyc Timing Specifications PCI Bus InterfaceSymbol Parameter a PCI 66 MHz PCI 33 MHz Units Min Max PCI Bus Interface Clock ParametersPCI Bus Interface Timing Parameters Symbol Parameter PCI 66MHz PCI 33 MHz Units Min MaxVTL Symbol Parameter PCI 66 MHz UnitPCI Bus Interface Timing Measurement Conditions VTHInch max Point 50 pF PinInch max Point 1kΩ 10 pF Rise and Fall Times Link Interface TimingEeprom Interface Date Code Device Identification82540EP Product Name YywwPackage Information DatasheetThermal resistance, junction-to-ambient Thermal SpecificationsThermal Characteristics Symbol Parameter Value at specified airflow m/s UnitsPinout Information Eeprom and Serial Flash Interface Signals Power Management SignalsImpedance Compensation Signals SMB SignalsAnalog Power Signals PHY SignalsTest Interface Signals Digital Power SignalsLanpwrgood Smbclk Grounds and No Connect SignalsSignal Names in Pin Order Sheet 1 Signal Name PinCLKRUN# Smbdata GND Signal Names in Pin Order Sheet 2RST# SMBALRT# M66EN REQ# CBE3#CLK VIO TRDY# Zpcomp Signal Names in Pin Order Sheet 3IRDY# FRAME# CBE2# GND PAR PERR# GNT# Signal Names in Pin Order Sheet 4STOP# INTA# DEVSEL# Zncomp CBE0# PCIAD5 GND PCIAD1 Clkview FLCE# Eesk Signal Names in Pin Order Sheet 5CBE1# Vddo P12 Signal Names in Pin Order Sheet 6PCIAD9 PCIAD7 PCIAD4 PCIAD8 PCIAD6 PCIAD3 PCIAD2 Eecs GND Flso EediC D E F G H J K L M N P Visual Pin Reference