Networking Silicon — 82540EP
3.6Test Interface Signals
Symbol | Type | Name and Function | |
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JTAG_TCK | I | JTAG Clock. | |
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JTAG_TDI | I | JTAG TDI. | |
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JTAG_TDO | O | JTAG TDO. | |
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JTAG_TMS | I | JTAG TMS. | |
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JTAG_ | I | JTAG Reset. This is an active low reset signal for JTAG. This signal should be | |
TRST# | terminated using a | ||
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TEST | I | Factory Test Pin. | |
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CLKVIEW | O | Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance testing. | |
The clock is selected by register programming. | |||
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3.7Power Supply Connections
3.7.1Digital Supplies
Symbol | Type |
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VDDO | P | 3.3 | V I/O Power Supply. |
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DVDD | P | 1.5 | V Digital Core Power Supply. |
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3.7.2Analog Supplies
Symbol | Type | Name and Function |
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AVDDH | P | 3.3 V Analog Power Supply. |
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AVDDL | P | 2.5 V Analog Power Supply. |
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Datasheet | 15 |