Intel 82540EP manual HostOffloading, PHY Specific Features

Page 12

82540EP — Networking Silicon

2.3PHY Specific Features

 

Features

 

 

Benefits

 

 

 

 

 

Integrated PHY for 10/100/1000 Mbps full and half

Smaller footprint and lower power dissipation

 

duplex operation

 

 

compared to multi-chip MAC and PHY solutions

 

 

 

 

 

IEEE 802.3ab Auto-Negotiation support

• Automatic link configuration including speed,

 

 

duplex, and flow control

 

 

 

 

 

 

 

 

 

IEEE 802.3ab PHY compliance and compatibility

• Robust operation over the installed base of

 

 

Category-5 (CAT-5) twisted pair cabling

 

 

 

 

 

 

 

 

 

State-of-the-art DSP architecture implements digital

Robust performance in noisy environments

 

adaptive equalization, echo cancellation, and cross-

Tolerance of common electrical signal

 

talk cancellation

 

 

impairments

 

 

 

 

 

PHY ability to automatically detect polarity and cable

Easier network installation and maintenance

 

lengths and MDI versus MDI-X cable at all speeds

End-to-end wiring tolerance

 

 

 

 

 

 

 

 

 

 

 

Features

 

 

Benefits

 

 

 

 

 

Transmit and receive IP, TCP and UDP checksum off-

Lower CPU utilization

 

loading capabilities

 

 

 

 

 

 

 

 

 

 

 

 

• Increased throughput and lower CPU utilization

 

Transmit TCP segmentation

 

Large send offload feature (in Microsoft*

 

 

 

 

Windows* XP) compatible

 

 

 

 

 

 

 

• 16 exact matched packets (unicast or multicast)

 

 

 

4096-bit hash filter for multicast frames

 

Advanced packet filtering

 

Promiscuous (unicast and multicast) transfer

 

 

 

 

mode support

 

 

 

• Optical filtering of invalid frames

 

 

 

 

 

IEEE 802.1q VLAN support with VLAN tag insertion,

• Ability to create multiple virtual LAN segments

 

stripping and packet filtering for up to 4096 VLAN tags

 

 

 

 

 

 

 

 

Descriptor ring management hardware for transmit

• Optimized fetching and write-back mechanisms for

 

 

efficient system memory and PCI bandwidth

 

and receive

 

 

 

 

 

usage

2.4

HostOffloading

Features

 

 

 

16 KByte jumbo frame support

 

High throughput for large data transfers on

 

 

 

 

networks supporting jumbo frames

 

 

 

 

 

Interrupt coalescing (multiple packets per interrupt)

• Increased throughput by reducing interrupts

 

 

generated by transmit and receive operations

 

 

 

 

 

 

 

 

 

6

Datasheet

Image 12
Contents 82540EP Gigabit Ethernet Controller Revision AprilDatasheet Date Revision 82540EP Networking Silicon Contents 82540EP Networking Silicon Introduction Mdio TX MACRX MAC Acpi LEDDocument Scope Reference DocumentsProduct Code 82540EP Networking Silicon PCI Features MAC Specific FeaturesFeatures Benefits Application flexibility for LAN on MotherboardPHY Specific Features HostOffloadingManageability Features A server management processorAdditional Device Features Technology FeaturesSignal Type Definitions PCI Address, Data and Control SignalsSymbol Type Name and Function PCI Bus InterfacePAR FRAME# STSIRDY# STS TRDY# STSArbitration Signals Interrupt SignalSystem Signals Error Reporting SignalsEeprom and Serial Flash Interface Signals Power Management SignalsImpedance Compensation Signals SMB SignalsMiscellaneous Signals LED SignalsOther Signals Analog XTAL1XTAL2 Test Interface Signals Power Supply ConnectionsDigital Supplies Analog SuppliesControl Signals Ground and No ConnectsGND CTRL15Absolute Maximum Ratings Recommended Operating ConditionsAbsolute Maximum Ratingsa Recommended Operating Conditions a Sheet 1DC Specifications DC CharacteristicsPower Specifications D0a Recommended Operating Conditions a Sheet 2Power Specifications D3cold Power Specifications Dr UninitializedPower Specifications Complete Subsystem O Characteristics Symbol Parameter Condition Min Typ Max= V SS AC Characteristics Timing Specifications PCI Bus Interface Symbol Parameter a PCI 66 MHz PCI 33 MHz Units Min MaxPCI Bus Interface Clock Parameters TcycSymbol Parameter PCI 66MHz PCI 33 MHz Units Min Max PCI Bus Interface Timing ParametersSymbol Parameter PCI 66 MHz Unit PCI Bus Interface Timing Measurement ConditionsVTH VTLPin Inch max Point 1kΩ 10 pFInch max Point 50 pF Link Interface Timing Eeprom InterfaceRise and Fall Times Device Identification 82540EP Product NameYyww Date CodeDatasheet Package InformationThermal Specifications Thermal CharacteristicsSymbol Parameter Value at specified airflow m/s Units Thermal resistance, junction-to-ambientPinout Information Power Management Signals Impedance Compensation SignalsSMB Signals Eeprom and Serial Flash Interface SignalsPHY Signals Test Interface SignalsDigital Power Signals Analog Power SignalsGrounds and No Connect Signals Signal Names in Pin Order Sheet 1Signal Name Pin Lanpwrgood SmbclkSignal Names in Pin Order Sheet 2 RST# SMBALRT#M66EN REQ# CBE3# CLKRUN# Smbdata GNDSignal Names in Pin Order Sheet 3 IRDY# FRAME# CBE2# GNDCLK VIO TRDY# Zpcomp Signal Names in Pin Order Sheet 4 STOP# INTA# DEVSEL# ZncompPAR PERR# GNT# Signal Names in Pin Order Sheet 5 CBE1#CBE0# PCIAD5 GND PCIAD1 Clkview FLCE# Eesk Signal Names in Pin Order Sheet 6 PCIAD9 PCIAD7 PCIAD4PCIAD8 PCIAD6 PCIAD3 PCIAD2 Eecs GND Flso Eedi Vddo P12Visual Pin Reference C D E F G H J K L M N P