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| 82540EP Architecture |
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| Flash Interface |
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| MDI |
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| (Copper) |
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| Target | Control, Status |
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| PHY | Interface | ||
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| & Interrupt | Flash | MDIO |
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| Control |
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| Registers |
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| Target Logic |
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| GMII |
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| PCI |
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| MAC Core |
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| DMA |
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| Tx |
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| Core |
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| TX |
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PCI |
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| TX MAC |
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| Arb |
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PCI I/F |
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| TX |
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| Out |
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i/f | read |
| AlignmentData |
| BufferPacketInterface | RegisterCSR Access | DataTX |
| RX Data |
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| engine |
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| descriptor | TX |
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| TX |
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| Master |
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| engine |
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| Link |
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| write |
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| FIFOs |
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| Flow |
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| RX MAC |
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| FIFO |
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| Ctrl |
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| RX |
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| Master |
| descriptor | RX |
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| FIFO |
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| FIFOs |
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| RX |
| RX Data |
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| In |
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| Filter |
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| (Many | ACPI | LED |
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| blocks) |
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| CSR Register |
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| Clock / Reset |
| 64K bytes |
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| Access |
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| HW |
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| EEPROM |
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Silicon |
| Default |
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| Manageability |
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| Configs | Packet Buffer |
| Mgmt | ASF | Statistics |
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| FIFOs |
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| SMBus Interface |
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Datasheet
Figure 1. Gigabit Ethernet Controller Block Diagram
2