Intel 82540EP manual Introduction

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Networking Silicon — 82540EP

1.0Introduction

The Intel® 82540EP Gigabit Ethernet Controller is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the Intel® 82540EP allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs

The Intel® 82540EP integrates Intel’s fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.2 compliant interface capable of operating at 33 or 66 MHz.

The 82540EP also incorporates the CLKRUN protocol and hardware supported downshift capability to two or three-pair 100 Mb/s operation. These features optimize mobile applications.

The Intel® 82540EP’s on-board System Management Bus (SMB) port enables network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Forum (ASF), to be implemented using the 82540EP. In addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities with standardized interfaces.

The 82540EP Gigabit Ethernet Controller architecture is designed to deliver high performance and PCI bus efficiency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82540EP controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for efficient bus usage. The 82540EP caches up to 64 packet descriptors in a single burst for efficient PCI bandwidth use. A large 64 KByte on-chip packet buffer maintains superior performance as available PCI bandwidth changes. In addition, using hardware acceleration, the controller offloads tasks from the host controller, such as TCP/UDP/IP checksum calculations and TCP segmentation.

The 82540EP is packaged in a 15 mm2 196-ball grid array and is pin compatible with both the 82551QM 10/100 Mbps Fast Ethernet Multifunction PCI/CardBus Controller and the 82540EM Gigabit Ethernet Controller (which does not have added power saving features like CLKRUN).

Datasheet

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Contents Revision April 82540EP Gigabit Ethernet ControllerDatasheet Date Revision 82540EP Networking Silicon Contents 82540EP Networking Silicon Introduction Acpi LED MdioTX MAC RX MACReference Documents Document ScopeProduct Code 82540EP Networking Silicon Application flexibility for LAN on Motherboard PCI FeaturesMAC Specific Features Features BenefitsHostOffloading PHY Specific FeaturesA server management processor Manageability FeaturesTechnology Features Additional Device FeaturesPCI Bus Interface Signal Type DefinitionsPCI Address, Data and Control Signals Symbol Type Name and FunctionTRDY# STS PARFRAME# STS IRDY# STSError Reporting Signals Arbitration SignalsInterrupt Signal System SignalsSMB Signals Eeprom and Serial Flash Interface SignalsPower Management Signals Impedance Compensation SignalsLED Signals Miscellaneous SignalsOther Signals XTAL1 AnalogXTAL2 Analog Supplies Test Interface SignalsPower Supply Connections Digital SuppliesCTRL15 Control SignalsGround and No Connects GNDRecommended Operating Conditions a Sheet 1 Absolute Maximum RatingsRecommended Operating Conditions Absolute Maximum RatingsaRecommended Operating Conditions a Sheet 2 DC SpecificationsDC Characteristics Power Specifications D0aPower Specifications Dr Uninitialized Power Specifications D3coldPower Specifications Complete Subsystem Symbol Parameter Condition Min Typ Max O Characteristics= V SS AC Characteristics Tcyc Timing Specifications PCI Bus InterfaceSymbol Parameter a PCI 66 MHz PCI 33 MHz Units Min Max PCI Bus Interface Clock ParametersPCI Bus Interface Timing Parameters Symbol Parameter PCI 66MHz PCI 33 MHz Units Min MaxVTL Symbol Parameter PCI 66 MHz UnitPCI Bus Interface Timing Measurement Conditions VTHInch max Point 1kΩ 10 pF PinInch max Point 50 pF Eeprom Interface Link Interface TimingRise and Fall Times Date Code Device Identification82540EP Product Name YywwPackage Information DatasheetThermal resistance, junction-to-ambient Thermal SpecificationsThermal Characteristics Symbol Parameter Value at specified airflow m/s UnitsPinout Information Eeprom and Serial Flash Interface Signals Power Management SignalsImpedance Compensation Signals SMB SignalsAnalog Power Signals PHY SignalsTest Interface Signals Digital Power SignalsLanpwrgood Smbclk Grounds and No Connect SignalsSignal Names in Pin Order Sheet 1 Signal Name PinCLKRUN# Smbdata GND Signal Names in Pin Order Sheet 2RST# SMBALRT# M66EN REQ# CBE3#IRDY# FRAME# CBE2# GND Signal Names in Pin Order Sheet 3CLK VIO TRDY# Zpcomp STOP# INTA# DEVSEL# Zncomp Signal Names in Pin Order Sheet 4PAR PERR# GNT# CBE1# Signal Names in Pin Order Sheet 5CBE0# PCIAD5 GND PCIAD1 Clkview FLCE# Eesk Vddo P12 Signal Names in Pin Order Sheet 6PCIAD9 PCIAD7 PCIAD4 PCIAD8 PCIAD6 PCIAD3 PCIAD2 Eecs GND Flso EediC D E F G H J K L M N P Visual Pin Reference
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