Intel 8051 manual Ii~O,.R~~~~~~

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8051 Architectural Specification and Functional Description

time is IllS and the access times required from stable address and from read (RD) or write (WR) command are approximately 600ns and 250ns respectively.

2.1.2.3 TIMER/EVENT COUNTERS

The 8051 contains two 16-bit counters for measuring time intervals, measuring pulse widths, counting events and generating precise, periodic interrupt requests. Each can be programmed independently to operate similar to an 8048 8-bit timer with divide by 32 prescaler or 8-bit counter with divide by 32 prescaler (Mode 0), as a 16-bit time-interval or event counter (Mode I), or as an 8-bit time-interval or event counter with automatic reload upon overflow (Mode 2).

Additionally, counter 0 can be programmed to a mode that divides it into one 8-bit time-interval or event counter and one 8-bit time-interval counter (Mode 3).

When counter 0 is in Mode 3, counter I can be programmed to any of the three aforementioned modes, although it cannot set an interrupt request flag or generate an interrupt. This mode is useful because counter I's over- flow can be used to pulse the serial port's transmission-rate generator. Along with their multiple operating modes and 16-bit precision, the counters can also handle very high input frequencies. These range from 0.1 MHzto 1.0 MHz (for 1.2 MHz to 12 MHz crystal) when programmed for an input that is a division by 12 of the oscillator frequency and from 0 Hz to an upper limit of 50 KHz to 0.5 MHz (for 1.2 MHz to 12 MHz crystal) when programmed for external inputs. Both· internal and external inputs can be gated to the counter by a second external source for directly measuring pulse widths.

The counters are started and stopped under software control. Each counter sets its interrupt request flag when it overflows from all ones to aU zeros (or auto-reload value). The operating modes and input sources are summarized in Figures 2.4A and 2.4B. The effects of the configuration flags and the status flags are shown in Figures 2.5A and 2.5B.

COUNTER/TIMER RUN

GATE

INTO --~=-~l:'~>-"t"--r-\--J====j~:J

TO------~

CRYSTAL

OSCILLATOR

$

OVERFLOW

~_--I~(INTERRUPT

EXTERNAL-.

SOURCE

REQUEST)

 

FLAG 0

8048 TIMER/COUNTER

16-BIT TIMER/COUNTER

8-BIT AUTO-RELOAD TIMER/COUNTER

CRYSTAL

°ii~O,.R__~~~~~__~

 

 

OVERFLOW

EXTSOEURRNCALE - .

1---4t----I~ (INTERRUPT

 

 

REQUEST)

 

 

FLAG 1

8048 TIMER/COUNTER

 

16-BIT TIMER/COUNTER

PULSE TO

8-BIT AUTO-RELOAD TIMER/COUNTER

 

 

SERIAL PORT

Figure 2.4.A. Timer/Event Counter

 

 

Modes 0, 1, and 2

 

 

CRYSTAL

CRYSTAL

 

 

OSCilLATOR

OSCILLATOR

 

EXTERNAL ___$

 

OVERFLOW

 

(INTERRUPT

 

REQUEST)

 

SOURCE

 

FLAG 1

 

 

OVERFLOW

 

 

 

 

 

L--____--I~(INTERRUPT

 

 

 

REQUEST)

8-BIT TIMER/COUNTER

8-BIT TIMER

FLAG 0

 

CRYSTAL

 

 

 

OSCilLATOR

 

 

 

$

 

 

EX;5~:~~'"

 

 

8048 TIMER/COUNTER

 

PULSE TO

16-BIT TIMER/COUNTER

 

8-BIT AUTO-RELOAD TIMER/COUNTER

SERIAL PORT

Figure 2.4.8. Timer/Event Counter Mode 3

INTERRUPT

REQUEST

COUNTER 0

MODE 0: 8-BIT TIMER WITH PRESCALER/8-BIT COUNTER

WITH PRESCAlER

>----fMODE 1: 16-BIT TIMER/COUNTER

MODE 2: 8-BIT AUTO-RELOAD TIMER/COUNTER

MODE 3: 8-BIT TIMER/COUNTER (TlO)

XTAl1

Figure 2.S.A. Timer/Counter 0 Control and Status Flag Circuitry

AFN-01488A-l0

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Contents Architectural Specification ICE SINGLE-COMPONENT 8-BIT Microcomputer Architectural Specification and Functional DescriptionContents Architectural Overview Enhancing the 8048 ARCHITEC- Ture for the 80s AbstractIntelscomplete Line of SINGLE-CHIP Microcomputers MACRO-VIEW of the 8051 Archi Tecture On-Chip Peripheral Functions Architectural Speciffcation ancrFunctionaJ DescrlpfionRequest Microcomputer Expansion Components Ii~O,.R~~~~~~ ~ J -r-r ~r~ r =fJ ~~~--------~--~--~---I~ Architectural Specification and Functional DescriptionInternal Data Memory Instruction DecoderProgram Counter · t1 Boolean Processor Arithmetic SectionProgramControl Section Oscillator and Timing CircuitryParallel I/O Ports Operand Addressing~~143 136 ~ Data Transfer Operations Data Manipulation18. External Data Memory Move Operations Logic Operations21. Internal Data Memory Logic Operations Arithmetic OperationsREGplSCTER 14e--I-~--I~IMMEDArE,.j Organization of the Instruction Set Instruction SeT What the Instruction Set IsData Transfer Control Transfer 33.A Operand Addressing Modes Operand Addressing Modes & Associated OperationsMOV Interrupt SystemTFI TCON.7 External Interrupts Ports and I/O PinsAccessing External Memory Accessing External Memory-Bus Cycle Timing TsU~l ArcnneCtural specification and Functional DescriptionAccessing External Memory-Opera- tion of Ports CDV Configuring the Timer/Counter Input TIMER/COUNTERTimer/Counter Mode Selection Serial Channel 47. Uart Interfacing Technique SCON.O Operating ModesTransmission Rate Generation Uart Error ConditionsSerial Frame Power Down Standby Operation of Internal RAM Processor Reset and InitializationEprom Programming Vee RSTNpD 8051 Instruction SET Summary Instructions That Affect Flag SettingsAll mnemonics copyrighted@ Intel Corporation