Intel 8051 manual Logic Operations, External Data Memory Move Operations

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8051 Architectural Specification and Functional Description

REGISTER

DIRECT

R7-RO

Data

REGISTER

A

REGISTER

A

REGISTER·INDIRECT

REGISTER-INDIRECT

@R1,@RO

@DP

(EXT DATA 0-255)

(EXT DATA 0-64K)

REGISTER-INDIRECT

@R1,@RO

Figure 2.18. External Data Memory Move Operations

can be moved to any of these locations. Of particular interest is the Direct Address to Direct Address move which permits the value in a port to be moved to the Internal Data RAM without using any RB registers or the accumulator. The Data Pointer register can be loaded with a double-byte immediate value. Also, the 8051's Boolean Processor can move any Direct Addressed bit to or from the carry flag.

The A register can be exchanged with a register in the selected Register Bank, with a Register-Indirect Addressed byte in the Internal Data RAM or with a Direct Addressed byte in the Internal Data RAM or Special Function Reg- ister. The least significant nibble of the A registt;r can also be exchanged with the least significant nibble of a Register- Indirect Addressed byte in the Internal Data RAM. The exchange operation is shown in Figure 2.20

Figure 2.20. Internal Data Memory Exchange Operations

2.5.2 Logic Operations

The 8051 permits the logic operations of and, or, and exlusive-or to be performed on the A register by a second operand which can be immediate value, a register in the selected Register Bank, a Register-Indirect Addressed byte of Internal Data RAM ora Direct Addressed byte of Internal Data RAM or Special Function Register. In addition, these logic operations can be performed on a Direct Addressed byte of the Internal Data RAM or Special Function Register using the A register as the second operand. Also, use of Immediate Addressing with Direct Addressing permits these logic operations to set, clear or complement any bit anywhere in the Internal Data RAM or Special Function Registers without

REGISTER

DIRECT

REGISTER

C

Data

DPTR

16

REGISTER

R7-RO

DIRECT

IMMEDIATE

Data

# data

REGISTER

REGISTER-INDIRECT

REGISTER-INDIRECT

A

@R1,@RO

@SP

Figure 2.19. Internal Data Memory Move Operations

AFN-01488A-19

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Contents Architectural Specification ICE Architectural Specification and Functional Description SINGLE-COMPONENT 8-BIT MicrocomputerContents Architectural Overview Enhancing the 8048 ARCHITEC- Ture for the 80s AbstractIntelscomplete Line of SINGLE-CHIP Microcomputers MACRO-VIEW of the 8051 Archi Tecture Architectural Speciffcation ancrFunctionaJ Descrlpfion On-Chip Peripheral FunctionsRequest Microcomputer Expansion Components Ii~O,.R~~~~~~ ~ J -r-r ~r~ r =fJ Architectural Specification and Functional Description ~~~--------~--~--~---I~Internal Data Memory Instruction DecoderProgram Counter · t1 Arithmetic Section ProgramControl SectionOscillator and Timing Circuitry Boolean Processor Operand Addressing Parallel I/O Ports~~143 136 ~ Data Manipulation Data Transfer OperationsLogic Operations 18. External Data Memory Move OperationsArithmetic Operations 21. Internal Data Memory Logic OperationsREGplSCTER 14e--I-~--I~IMMEDArE,.j Instruction SeT What the Instruction Set Is Organization of the Instruction SetData Transfer Control Transfer Operand Addressing Modes & Associated Operations 33.A Operand Addressing ModesInterrupt System MOVTFI TCON.7 Ports and I/O Pins External InterruptsAccessing External Memory Accessing External Memory-Bus Cycle Timing TsU~l ArcnneCtural specification and Functional DescriptionAccessing External Memory-Opera- tion of Ports CDV Configuring the Timer/Counter Input TIMER/COUNTERTimer/Counter Mode Selection Serial Channel 47. Uart Interfacing Technique Operating Modes SCON.OTransmission Rate Generation Uart Error ConditionsSerial Frame Processor Reset and Initialization Power Down Standby Operation of Internal RAMEprom Programming Vee RSTNpD Instructions That Affect Flag Settings 8051 Instruction SET SummaryAll mnemonics copyrighted@ Intel Corporation