8051 Architectural Specification and Functional Description
CARRY | DECIMAL | PARITY | |
CARRY | |||
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SYMBOLIC
REGISTER:
USER | REGISTER BANK | RESERVED |
FLAG | SELECT |
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PSW.7: CY: Carry Flag (also the C register)
PSW.6: AC:
PSW.2: OV: Overflow Flag
PSW.O: P: Parity Flag
PSW.5: FO: User Flag 0
PSW.I: reserved
PSW.4: RSI: Register Select MSb
PSW.3: RSO: Register Select LSb
Unless otherwise stated, the instructions obey these rules: CY is set if the operation results in a carry out of (during addition) or a borrow into (during sub- traction) the
AC is set if the operation results in a carry out of the
o V is set if the operation results in a carry into the
P is set if the module 2 sum of the eight bits in the accumulator is I (odd parity); otherwise P is cleared (even parity). When a value is written to the PSW register, the P bit remains unchanged, as it always reflects the parity of A.
Addition. Four addition operations are provided:
INC (increment) performs an addition of the source operand and one (I) and returns the result to the operand.
ADD performs an addition between the A register and the second source operand and returns the result to the A register.
ADDC (add with carry) performs an addition between the A register and the second source operand; adds one (1) if the C flag is found pre- viously set and returns the result to register A.
DA
Subtraction. Two subtraction operations are provided: SUBB (subtract with borrow) performs a subtrac- tion of the second source operand from the first
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operand (the accumulator), subtracts one (I) if the C flag is found previously set and returns the result to the A register.
DEC (decrement) performs a subtraction of one
(1)from the source operand and returns the results to the operand.
Multiplication.
MUL performs an unsigned multiplication of the A register by the B register, returning a double- byte result. Register A receives the
Division.
DIV performs an unsigned division of the A register by the B register and returns the integer quotient to register A and returns the fractional remainder to the B register. Division by zero leaves indeterminate data in registers A and B and sets OV, otherwise OV is cleared. C is cleared. AC remains unaltered.
CONTROL TRANSFER
There are' three classes of control transfer operations: unconditional calls, returns and jumps; conditional jumps; and interrupts. All control transfer operations cause, some upon a specific condition, the program execution to continue at a
Unconditional Calls, Returns and Jumps. Unconditional calls, returns and jumps transfer control from the current value of the Program Counter to the target address. Both direct and indirect transfers are supported. The three transfer operations are described below.
ACALL and LCALL push the address of the next instruction onto the stack (PCL to
RET transfers control to the return address saved on the stack by a previous call operation and decrements the SP register by two (2) to adjust the SP for the popped address.
AJMP, LJMP and SJMP transfer control tothe target operand. The operation of AJ M P and LJMP are analogous to ACALL and LCALL.