Intel 8051 manual All mnemonics copyrighted@ Intel Corporation

Page 43

8051 Architectural Specification and Functional Description

Arithmetic

 

 

Oscillator

 

 

 

Mnemonic

Description

Bytes

Periods

ADD A.Rn

Add register to A

I

12

"ADD A.data

Add direct byte to A

2

12

ADDA.@Ri

Add indirect RAM to A

I

12

ADDA./Idata

Add immediate data to A

2

12

ADDC A.Rn

Add register and carry flag to A

I

12

*ADDC A.data

Add direct byte aild carry flag

2

12

 

toA

 

 

ADDC A.@Ri

Add indirect RAM and carry

 

12

 

flag to A

 

 

ADDC A./Idata

Add immediate data and carry

2

12

 

flag to A

 

 

ContrOl Trans'er(Branch)

Mnemonic

Description

AJMP addrll

Absolute Jump

"LJMP addrl6

Long Jump

"SJMP rei

Short Jump

"JMP @A+DPTR Jump indirect relative to

 

the DPTR

JZ rei

Jump if A is zero

JNZ rei

Jump if A is not zero

JC rei

Jump if carry is set

JNC rei

Jump if carry is not set

"JD bit. rei

Jump relative if direct bit

 

is set

Oscillator

Byt..

Periods

2

24

3

24

2

24

 

24

2

24

2

24

2

24

2

24

3

24

"SUBD A.Rn

Subtract register and carry flag

 

12

 

from A

 

 

"SUBD A.data

Subtract direct byte and carry

2

12

 

flag from A

 

 

"SUBD A.@Ri

Subtract indirect RA M and

 

12

 

carry flag from A

 

 

"SUBD A./Idata

Subtract immediate data aild

2

12

 

carry flag from A

 

 

INCA

Increment A

 

12

INC Rn

Increment register

 

12

"INC data

Increment direct byte

2

12

INC@Ri

Increment indirect RAM

 

12

DECA

Decrement A

I

12

DEC Rn

Decrement register

I

12

"DEC data

Decrement direct byte

2

12

"DEC@Ri

Decrement indirect RAM

 

12

"INC DPTR

Increment Data Pointer

 

24

'MUL AB

Multiply A times D

 

48

'DIV AD

Divide A by D

 

48

DAA

Decimal add Adjust of A

 

12

Other

 

 

Oscillator

 

 

 

Mnemonic

D..crlptlon

Byt..

Periods

NOP

No Operation

I

12

"JNB bit. rei

Jump relative if direct bit

3

24

 

is not set

 

 

"J DC bit.rel

Jump relative if direct bit

3

24

 

is ser. then clear bit

 

 

"CJNE A.data.rel

Compare direct byte to A

3

24

 

& Jump if not Eq.

 

 

 

See Note a.

 

 

'CJNE A.lldata.rel Compare immed. to A & Jump

3

24

 

if not Eq. See Note a.

 

 

'CJNE Rn.lldata.

Compare immed. to reg &

3

24

rei

Jump if not Eq. See Note a.

 

 

'CNJE @Ri.

Compare immed. to indirect

3

24

IIdata.rel

RAM & Jump if not Eq.

 

 

 

See Note a.

 

 

DJNZ Rn.rel

Decrement register & Jump

3

24

 

if not zero

 

 

'DJNZ data. rei

Decrement direct byte &

3

24

 

Jump if not zero

 

 

Note a) Set C if the first operand is less than the second operand; else clear

Control Trans'er(Subroutine)

 

Oscillator

 

 

 

Mnemonic

Description

Bytes

Periods

ACALL addrll

Absolute Subroutine Call

2

24

LCALL addrl6

Long Subroutine Call

3

24

RET

Return from Subroutine Call

 

24

RETI

Return from Interrupt Call

 

24

All mnemonics copyrighted@ Intel Corporation 1980.

AFN-01488A-42

38

Image 43
Contents Architectural Specification ICE SINGLE-COMPONENT 8-BIT Microcomputer Architectural Specification and Functional DescriptionContents Architectural Overview Intelscomplete Line of SINGLE-CHIP Microcomputers AbstractEnhancing the 8048 ARCHITEC- Ture for the 80s MACRO-VIEW of the 8051 Archi Tecture On-Chip Peripheral Functions Architectural Speciffcation ancrFunctionaJ DescrlpfionRequest Microcomputer Expansion Components Ii~O,.R~~~~~~ ~ J -r-r ~r~ r =fJ ~~~--------~--~--~---I~ Architectural Specification and Functional DescriptionProgram Counter Instruction DecoderInternal Data Memory · t1 Boolean Processor Arithmetic SectionProgramControl Section Oscillator and Timing CircuitryParallel I/O Ports Operand Addressing~~143 136 ~ Data Transfer Operations Data Manipulation18. External Data Memory Move Operations Logic Operations21. Internal Data Memory Logic Operations Arithmetic OperationsREGplSCTER 14e--I-~--I~IMMEDArE,.j Organization of the Instruction Set Instruction SeT What the Instruction Set IsData Transfer Control Transfer 33.A Operand Addressing Modes Operand Addressing Modes & Associated OperationsMOV Interrupt SystemTFI TCON.7 External Interrupts Ports and I/O PinsAccessing External Memory Accessing External Memory-Opera- tion of Ports TsU~l ArcnneCtural specification and Functional DescriptionAccessing External Memory-Bus Cycle Timing CDV Timer/Counter Mode Selection TIMER/COUNTERConfiguring the Timer/Counter Input Serial Channel 47. Uart Interfacing Technique SCON.O Operating ModesSerial Frame Uart Error ConditionsTransmission Rate Generation Power Down Standby Operation of Internal RAM Processor Reset and InitializationEprom Programming Vee RSTNpD 8051 Instruction SET Summary Instructions That Affect Flag SettingsAll mnemonics copyrighted@ Intel Corporation