Intel 8051 manual Cdv

Page 32

8051 Architectural Specification and Functional Description

T12

OSC

ALE

PORT 2

PORTO

ALE

FLOAT

	Figure 2.41. Program Memory Read Cycle Timing
CDV	\0	I
V

RD	~0

0

PORT 2		X			ADDRESS A15-Aa
PORT 2					ADDRESS A15-Aa
	INST Irl FLOAT		0	0	(6)
PORTO	INST Irl FLOAT		A7-Ao	I FLOAT	>(	DATA IN
	I	I	I	I		I

Figure 2.42. Data Memory Read Cycle Timing

ALE		G::V		\
ALE
		II
				®	\0
			X	®
PORT 2			X		ADDRESS A15-Aa
PORT 2					ADDRESS A15-Aa
		IN IFLOAT		0	~
PORTO	INST			A7-Ao	D<	DATA OUT
				A7-Ao	D<	DATA OUT
		I	I	I		I	I
NOTE: In Figures 2.42 and 2.43 the Prior and Subsequent Machine Cycles access Program Memory.

CD 1/

®

I ADDRESS

FLOAT ORFLOAT

I

II

@II

0

ADDRESS

OR FLOAT

Figure 2.43. Data Memory Write Cycle Timing

AFN-01488A-31

27

Image 32

Contents Architectural Specification ICE Architectural Specification and Functional Description SINGLE-COMPONENT 8-BIT MicrocomputerContents Architectural Overview Enhancing the 8048 ARCHITEC- Ture for the 80s AbstractIntelscomplete Line of SINGLE-CHIP Microcomputers MACRO-VIEW of the 8051 Archi Tecture Architectural Speciffcation ancrFunctionaJ Descrlpfion On-Chip Peripheral FunctionsRequest Microcomputer Expansion Components Ii~O,.R~~~~~~ ~ J -r-r ~r~ r =fJ Architectural Specification and Functional Description ~~~--------~--~--~---I~Internal Data Memory Instruction DecoderProgram Counter · t1 Arithmetic Section ProgramControl SectionOscillator and Timing Circuitry Boolean ProcessorOperand Addressing Parallel I/O Ports~~143 136 ~ Data Manipulation Data Transfer OperationsLogic Operations 18. External Data Memory Move OperationsArithmetic Operations 21. Internal Data Memory Logic OperationsREGplSCTER 14e--I-~--I~IMMEDArE,.j Instruction SeT What the Instruction Set Is Organization of the Instruction SetData Transfer Control Transfer Operand Addressing Modes & Associated Operations 33.A Operand Addressing ModesInterrupt System MOVTFI TCON.7 Ports and I/O Pins External InterruptsAccessing External Memory Accessing External Memory-Bus Cycle Timing TsU~l ArcnneCtural specification and Functional DescriptionAccessing External Memory-Opera- tion of Ports CDV Configuring the Timer/Counter Input TIMER/COUNTERTimer/Counter Mode Selection Serial Channel 47. Uart Interfacing Technique Operating Modes SCON.OTransmission Rate Generation Uart Error ConditionsSerial Frame Processor Reset and Initialization Power Down Standby Operation of Internal RAMEprom Programming Vee RSTNpD Instructions That Affect Flag Settings 8051 Instruction SET SummaryAll mnemonics copyrighted@ Intel Corporation