Intel 8051 manual Architectural Overview

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CHAPTER 2 ARCHITECTURAL OVERVIEW AND

 

FUNCTIONAL DESCRIPTION (Continued)

 

2.10

Accessing External Memory

25

 

2.10.1 Operation of Ports

26

 

2.10.2

Bus Cycle Timing

26

2.11

TimerlCounter

..........................

28

 

2.11.1

TIC Mode Selection

28

 

2.11.2

Configuring the TIC Input

28

 

2.11.3

TIC Operation

29

 

2.11.4 Reading and Reloading the TIC .... 29

2.12

Serial Channel

..........................

29

 

2.12.1 Serial Port Control Register and

 

 

 

 

Serial Data Registers

'....

31

 

2.12.2

Operating Modes

31

 

 

2.12.2.1

Operating Mode O•....•••.

31

 

 

2.12.2.2

Operating Modes 1

 

 

 

 

 

through 3

32

 

2.12.3 The Serial Frame

32

 

2.12.4 Transmission Rate Generation ..... 32

 

2.12.5 UART Message Error Conditions ... 33

2.13

External Interface

33

 

2.13.1

Processor Reset and

 

 

 

 

Initialization

33

 

2.13.2 Power Down Operation of

 

 

 

 

Internal RAM

33

2.14

EPROM Programming

34

2.15

The 8051 as an Evolution of the 8048

34

2.16Development System and Software

 

Support

34

2.17

8051 Pin Description

35

Table 2.1

Instruction Set Summary

37

AFN-01488A-04

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Contents Architectural Specification ICE SINGLE-COMPONENT 8-BIT Microcomputer Architectural Specification and Functional DescriptionContents Architectural Overview Enhancing the 8048 ARCHITEC- Ture for the 80s AbstractIntelscomplete Line of SINGLE-CHIP Microcomputers MACRO-VIEW of the 8051 Archi Tecture On-Chip Peripheral Functions Architectural Speciffcation ancrFunctionaJ DescrlpfionRequest Microcomputer Expansion Components Ii~O,.R~~~~~~ ~ J -r-r ~r~ r =fJ ~~~--------~--~--~---I~ Architectural Specification and Functional DescriptionInternal Data Memory Instruction DecoderProgram Counter · t1 ProgramControl Section Arithmetic SectionOscillator and Timing Circuitry Boolean ProcessorParallel I/O Ports Operand Addressing~~143 136 ~ Data Transfer Operations Data Manipulation18. External Data Memory Move Operations Logic Operations21. Internal Data Memory Logic Operations Arithmetic OperationsREGplSCTER 14e--I-~--I~IMMEDArE,.j Organization of the Instruction Set Instruction SeT What the Instruction Set IsData Transfer Control Transfer 33.A Operand Addressing Modes Operand Addressing Modes & Associated OperationsMOV Interrupt SystemTFI TCON.7 External Interrupts Ports and I/O PinsAccessing External Memory Accessing External Memory-Bus Cycle Timing TsU~l ArcnneCtural specification and Functional DescriptionAccessing External Memory-Opera- tion of Ports CDV Configuring the Timer/Counter Input TIMER/COUNTERTimer/Counter Mode Selection Serial Channel 47. Uart Interfacing Technique SCON.O Operating ModesTransmission Rate Generation Uart Error ConditionsSerial Frame Power Down Standby Operation of Internal RAM Processor Reset and InitializationEprom Programming Vee RSTNpD 8051 Instruction SET Summary Instructions That Affect Flag SettingsAll mnemonics copyrighted@ Intel Corporation