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8051 Architectural Specification and Functional Description
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| TIMER |
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| TCON |
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| DPL |
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| SP |
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| 128·8 |
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| PCL |
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| REGISTER BANK 3 |
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| REGISTER BANK 2 |
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| CONTROL |
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| PLA |
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| REGISTER BANK 0 |
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| DRIVERS |
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| CONTROL |
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| ENGINE |
| Iv |
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| ~~ |
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| INSTRUCTION |
| VL |
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| DECODER |
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CIRCUITRY | q |
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t | + |
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osc |
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TIMING |
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| I | I | I |
| I |
| I |
| 1 | r |
x | X | E | A | P | D |
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| PORTO0 | |
T | T | A | L | S |
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| |||
A | A | / | E | E |
| PORT 3 |
| PORT2 |
| |||||
L | L | V | / | N | PORT 1 |
| D |
| D | |||||
1 | 2 | D | P |
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| D | R |
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G
4K ·8 NONE (8031) ROM (8051V EPROM (87511
DRIVERS
~~
I
~
17- ~
R V V
S C S
T C S
/
V
P
D
Figure 2.11. 8051 Family Functional Block Diagram
10