3.4.2. Trigger Coupling
Trigger coupling is used to select the coupling mode applied to the input of the trigger circuitry. Modes available include AC LF Reject and DC. The AC LF Reject mode couples signals capacitively and removes the input signal's DC component and signals below 50 KHz (50 Hz for
3.4.3. Trigger Level
The trigger level specifies the voltage at which the selected trigger source will produce a valid trigger. The trigger level is defined as a set voltage. Using the internal trigger, the level is set with respect to the midpoint voltage (Vm= – Offset voltage) of the digitizer’s vertical scale. Internal trigger level settings (expressed in %) must be within Vm ±
0.6FS (0.5 FS for
For most digitizers, the AC coupled mode is implemented with an
The
The
3.4.4. Edge Trigger Slope
The trigger slope defines which one of the two possible transitions will be used to initiate the trigger when it passes through the specified trigger level. Positive slope indicates that the signal is transitioning from a lower voltage to a higher voltage. Negative slope indicates the signal is transitioning from a higher voltage to a lower voltage.
3.4.5. Window Trigger
The
3.4.6. HF Trigger
The
3.4.7. Spike Stretcher
The trigger circuit of the 2 channels of the DP1400 also has a Spike Stretcher mode which ensures that even very short pulses are capable of generating triggers. This mode is useful if the time interval during which the trigger signal satisfies the threshold condition is less than 0.5 ns and the trigger frequency is less than 10 MHz. The trigger slope is positive in this mode.
3.4.8. DP1400 Multi-source Trigger
This digitizer permits triggers that require a pattern condition including one of the trigger channels and the external trigger. The trigger condition defined above, on each of the inputs, defines the TRUE/FALSE state of each input. These states can be logically combined with AND, OR, NAND, or NOR to define the overall trigger condition. Potential triggers can then occur on the FALSE to TRUE transitions of the combined signal.
There is a small (~ns) delay between the times at which two simultaneous inputs arrive at the logical element that defines the overall trigger condition. If necessary, this must be corrected for by cable delay on the external input; the delay will depend on the overall configuration and therefore must be determined by the user.
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