Texas Instruments PCI445X manual Socket Activity LEDs, MFUNC7±MFUNC0 Terminal Assignments

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System Features Selection

1.1.10 Socket Activity LEDs

Socket activity signals can be assigned on MFUNC4 (slot 1), MFUNC3 (slot 2), MFUNC5 (OHCI_LED), MFUNC6 (OHCI_LED), and MFUNC7 (OHCI_LED).

1.1.11 MFUNC7±MFUNC0 Terminal Assignments

After selecting required functions for the system, multifunction terminals MFUNC7±MFUNC0 are ready to be assigned. Texas Instruments offers Windows-based software, named TIROUTE.EXE, to assist with terminal assignment.

1.1.12 Miscellaneous Functions Description

1.1.12.1 Serialized Interrupt Control

Serialized interrupt signaling is described below.

Figure 1±2. Serialized Interrupt Signal

PCLK

IRQSER

 

 

 

 

 

START Frame

IRQ0

IRQ1

SMI

IRQ3

IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ10 IRQ11 IRQ12

PCLK

 

 

 

 

 

IRQSER

 

 

 

 

 

IRQ13 IRQ14 IRQ15 IOCHCK

INTA

INTB

INTC

INTD

STOP Frame

The start frame width may vary from four to eight PCI clock cycles. The STOP frame width is two clock cycles for quiet mode and three clock cycles for continuous mode. Default mode is continuous mode for all slave devices and a host device. PIIX4 does not support IRQ0, IRQ8, and IRQ13.

The PCI445X can generate serial IRQ frames for ISA and PCI interrupts. Below are related registers and their definitions.

￿INTMODE bits (device control register, PCI offset 92h, bits 2±1). Select interrupt mode

￿SER_STEP bits (system control register, PCI offset 80h, bits 31±30). Change PCI interrupt data frame (serial interrupts only)

￿INTRTIE bit (system control register, PCI offset 80h, bit 29). Tie CardBus PCI interrupts to INTA

￿TIEALL bit (system control register, PCI offset 80h, bit 28). Tie all PCI interrupts internally

Refer to the Serialized IRQ Support for PCI Systems specification, revision 6.0.

1.1.12.2 CSC Interrupt Routing for Windows Compatibility

The CSC interrupt routing control bit (diagnostic register, PCI offset 93h, bit 5) should be set to 1 (default) to keep Windows compatibility.

PCI445X Device

1-5

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Contents Implementation Guide Important Notice About This Manual Read This FirstCsr ±a /user/ti/simuboard/utilities Related Documentation From Texas Instruments Page Contents Viii Figures Tables Topic PCI445X Device±1. Typical System Architecture System Features Selection Distributed DMA Ddma Socket Power SwitchesOptional PCI Signals PCI and ISA Style InterruptSerialized Interrupt Control Socket Activity LEDsMFUNC7±MFUNC0 Terminal Assignments Miscellaneous Functions DescriptionMemory Burst R/W Operation Control CardBus Reserved Terminal SignalingPower Savings Mode Asynchronous CSC Interrupt GenerationZV Port Control and Auto Detect Function Socket Power Lock12.9 SMI 12.11VCC ProtectionPERR, SERR, and Lock System ImplementationClamping Rails PCI Bus InterfaceINTA, INTB, and Intc Prst PCI reset and Grst Global resetDamping resistor on Cclk terminal 4 2-Wire I2C Interface for EepromSocket power supply PC Card InterfaceEeprom ±1. Registers and Bits Loadable Through Serial EepromSample PCI445X Eeprom Data File System Implementation Zoomed Video ZV Interface 1 P2C Interface for TPS22X6 Power SwitchMiscellaneous Signals Interrupt Signaling Interface±2. PC Card Interface Pullup Resistor List² ³ Requirement of Pullup/Pulldown Resistors±4. Miscellaneous Terminals Pullup Resistor List ±3. PCI Bus Interface Pullup Resistor ListLPS ±5. Required Pullup/Pulldown ResistorsBios Considerations InitializationPCI Standard Registers Initialization PCI TI Proprietary Registers Initialization System Sleeping State ConsiderationDocking System Consideration Register save/restoreImportant Information Topic Global Reset Only Bits, PME Context BitsTable A±1.Global Reset Only Cleared Bits Global Reset Only Bits/PME Context BitsTable A±2.PME Context Bits Page PME and RI Behavior PME and RI Behavior Table B±1.CardBus Ctschg and Wake-Up Signals Truth TablePCI445X Buffer Types PCI445X Buffer Types Signal Name Terminal TypeACVS2 BCAD22 GND PHYDATA6 ZVUV4 TSO Buffer Type Description Table C±2. Buffer Type Abbreviations
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