Texas Instruments PCI445X manual Bios Considerations, Initialization

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System Implementation

1.4 BIOS Considerations

1.4.1Initialization

This section explains which registers require initialization, but does not discuss detailed information about the registers themselves. Refer to the corresponding specifications.

Reference white paper:

http://www.microsoft.com/hwdev/busbios/cardbus1.htm

1.4.1.1PCI Standard Registers Initialization

￿Command register (PCI offset 04h: 16-bit)

Set to 0007h (enables bus master control, memory space control, and I/O space control)

￿Cache line size register (PCI offset 0Ch: 8-bit)

Set to 08h (It is dependent on host-to-PCI bridge specification). It enables memory read line and memory read multiple command.

￿Latency timer (PCI offset 0Dh: 8-bit)

This register should reflect each PC Card requirement, but Windows does not do so. Therefore, system imlementers should determine the value. A detailed description of this register is in the PCI Local Bus Interface Specification. Typical setting for this register is 40h.

￿CardBus socket registers/ExCA base address (PCI offset 10h: 32-bit) It should be set to 0000 0000h (default).

￿CardBus latency timer register (PCI offset 1Bh: 8-bit)

Setup of this register is not required because the CardBus bus is a single-device bus, and the PCI445X device does not deassert CGNT until a transaction is finished. (It does not mean that the PCI445X device continues the transaction. The PCI445X device would terminate and disconnect or abort the transaction as required).

￿Memory and I/O windows (PCI offset 1Ch ± 3Fh)

All memory and I/O windows should be closed (set to base > limit).

￿Interrupt line register (PCI offset 3Ch: 8-bit) This register is set to FFh (default).

￿Subsystem vendor ID and subsystem ID registers (PCI offsets 40h and 42h: 16-bit/16-bit)

These registers can be set through EEPROM or BIOS. These registers are read-only as default. Before writing to the registers, the SUBSYSRW bit (system control register, PCI offset 80h, bit 5) should be set to 1. After setting up the registers, the SUBSYSRW bit should be set 0 to protect

PCI445X Device

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Contents Implementation Guide Important Notice About This Manual Read This FirstCsr ±a /user/ti/simuboard/utilities Related Documentation From Texas Instruments Page Contents Viii Figures Tables Topic PCI445X Device±1. Typical System Architecture System Features Selection Optional PCI Signals Socket Power SwitchesPCI and ISA Style Interrupt Distributed DMA DdmaMFUNC7±MFUNC0 Terminal Assignments Socket Activity LEDsMiscellaneous Functions Description Serialized Interrupt ControlPower Savings Mode CardBus Reserved Terminal SignalingAsynchronous CSC Interrupt Generation Memory Burst R/W Operation Control12.9 SMI Socket Power Lock12.11VCC Protection ZV Port Control and Auto Detect FunctionClamping Rails System ImplementationPCI Bus Interface PERR, SERR, and LockINTA, INTB, and Intc Prst PCI reset and Grst Global resetSocket power supply 4 2-Wire I2C Interface for EepromPC Card Interface Damping resistor on Cclk terminalEeprom ±1. Registers and Bits Loadable Through Serial EepromSample PCI445X Eeprom Data File System Implementation Zoomed Video ZV Interface 1 P2C Interface for TPS22X6 Power SwitchMiscellaneous Signals Interrupt Signaling Interface±2. PC Card Interface Pullup Resistor List² ³ Requirement of Pullup/Pulldown Resistors±4. Miscellaneous Terminals Pullup Resistor List ±3. PCI Bus Interface Pullup Resistor ListLPS ±5. Required Pullup/Pulldown ResistorsPCI Standard Registers Initialization Bios ConsiderationsInitialization PCI TI Proprietary Registers Initialization System Sleeping State ConsiderationDocking System Consideration Register save/restoreImportant Information Topic Global Reset Only Bits, PME Context BitsTable A±1.Global Reset Only Cleared Bits Global Reset Only Bits/PME Context BitsTable A±2.PME Context Bits Page PME and RI Behavior PME and RI Behavior Table B±1.CardBus Ctschg and Wake-Up Signals Truth TablePCI445X Buffer Types PCI445X Buffer Types Signal Name Terminal TypeACVS2 BCAD22 GND PHYDATA6 ZVUV4 TSO Buffer Type Description Table C±2. Buffer Type Abbreviations
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