Texas Instruments PCI445X manual System Features Selection

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System Features Selection

1.1 System Features Selection

This section explains selectable system features. Feature selection is required for GPIO and MFUNC terminal assignments and PCI445X register initialization. Detailed system implementation methods are described in the following sections. All functions cannot necessarily be used at the same time, because of the limitations of programmable multifunction terminals (i.e., MFUNC7±MFUNC0).

1.1.1Package Types

The Texas Instruments PCI445X device is offered in two package types: 256-terminal ball grid array (BGA) and 257-terminal MicroStar BGA. MicroStar BGAis a type of chip scale packaging (CSP).

1.1.2G_RST and PRST

The PCI445X device has two reset inputs, G_RST and PRST. G_RST resets all registers and state-machines; PRST resets registers that are not required to maintain context in a low power state (see Table A±1 and Table A±2). If the system does not support a wake-up event from D3-state (hot or cold), then these terminals can be tied together.

1.1.3PME and RI Signaling

For supporting a wake-up event, a power management event (PME) and/or an RI signal should be signaled to the system. PME is available only on the RI_OUT/PME terminal. RI_OUT is available on RI_OUT/PME or MFUNC7. PME and RI_OUT signals are usually connected to the south bridge or embedded controller (EC). Detailed PME and RI signal behavior is explained later.

1.1.4ZV Support

The PCI445X device has internal zoomed video (ZV) buffers. It can support three ZV sources, from two PC cards and one external source. Refer to the detailed implementation guide in Section 1.3.2. The PCI445X device has the ZV autodetect function for supporting a third external zoomed video source. ZVSTAT and ZVPCLK are required to support the third source. (The ZV autodetect function needs ZVPCLK for input, and ZVSTAT for enabling.) ZVSTAT can be assigned on the MFUNC0, MFUNC1, or MFUNC4 terminal.

1.1.5EEPROM for Subsystem Vendor and Subsystem ID Registers

Subsystem vendor ID and subsystem ID registers (PCI offsets 40h and 42h) can be loaded from EEPROM through a two-wire serial interface. These registers can be configured by BIOS if the PCI445X device is implemented on the motherboard, by setting the SUBSYSRW bit (system control register, PCI offset 80h, bit 5). EEPROM may be required for docking systems and is required for add-in cards. The EEPROM interface terminals SDA and SCL are

PCI445X Device

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Contents Implementation Guide Important Notice About This Manual Read This FirstCsr ±a /user/ti/simuboard/utilities Related Documentation From Texas Instruments Page Contents Viii Figures Tables Topic PCI445X Device±1. Typical System Architecture System Features Selection Optional PCI Signals Socket Power SwitchesPCI and ISA Style Interrupt Distributed DMA DdmaMFUNC7±MFUNC0 Terminal Assignments Socket Activity LEDsMiscellaneous Functions Description Serialized Interrupt ControlPower Savings Mode CardBus Reserved Terminal SignalingAsynchronous CSC Interrupt Generation Memory Burst R/W Operation Control12.9 SMI Socket Power Lock12.11VCC Protection ZV Port Control and Auto Detect FunctionClamping Rails System ImplementationPCI Bus Interface PERR, SERR, and LockINTA, INTB, and Intc Prst PCI reset and Grst Global resetSocket power supply 4 2-Wire I2C Interface for EepromPC Card Interface Damping resistor on Cclk terminalEeprom ±1. Registers and Bits Loadable Through Serial EepromSample PCI445X Eeprom Data File System Implementation Zoomed Video ZV Interface 1 P2C Interface for TPS22X6 Power SwitchMiscellaneous Signals Interrupt Signaling Interface±2. PC Card Interface Pullup Resistor List² ³ Requirement of Pullup/Pulldown Resistors±4. Miscellaneous Terminals Pullup Resistor List ±3. PCI Bus Interface Pullup Resistor ListLPS ±5. Required Pullup/Pulldown ResistorsInitialization Bios ConsiderationsPCI Standard Registers Initialization PCI TI Proprietary Registers Initialization System Sleeping State ConsiderationDocking System Consideration Register save/restoreImportant Information Topic Global Reset Only Bits, PME Context BitsTable A±1.Global Reset Only Cleared Bits Global Reset Only Bits/PME Context BitsTable A±2.PME Context Bits Page PME and RI Behavior PME and RI Behavior Table B±1.CardBus Ctschg and Wake-Up Signals Truth TablePCI445X Buffer Types PCI445X Buffer Types Signal Name Terminal TypeACVS2 BCAD22 GND PHYDATA6 ZVUV4 TSO Buffer Type Description Table C±2. Buffer Type Abbreviations
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