Texas Instruments PCI445X manual System Sleeping State Consideration

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System Implementation

against unexpected overwriting. The values are system and vendor dependent.

￿PC Card 16-bit I/F legacy mode base address register (PCI offset 44h: 32-bit)

Set to 0000 03E1h (16-bit mode) and set to 0000 0001 (CardBus mode) in response to a disable call.

￿Power management capabilities register (PCI offset A2h: 16-bit) If the system does not support VAUX in D3cold state, then clear bit 15.

￿Power management control/status register (PCI offset A4h: 16-bit)

Clear bit 15 by writing a 1. This should be done after all the other initialization for the PCI445X device is finished. Make sure that the PCI445X device is in the D0 state, especially after reboot.

1.4.1.2PCI TI Proprietary Registers Initialization

The registers listed below should be set up according to system requirements. Refer to Section 1.1.12.

￿System control register (PCI offset 80h: 32-bit)

￿Multimedia control register (PCI offset 84h: 8-bit)

￿GPIO3±GPIO0 control registers (PCI offset 88h ± 8Bh: 8-bit)

￿Multifunction routing register (PCI offset 8Ch: 32-bit)

￿Card control register (PCI offset 91h: 8-bit)

￿Device control register (PCI offset 92h: 8-bit)

￿Diagnostic register (PCI offset 93h: 8-bit)

￿DMA socket register 0 and 1 (PCI offset 94h, 98h: 32-bit)

￿GPE control/status register (PCI offset A8h: 16-bit)

￿ExCA identification and revision (ExCA offset 800h: 8-bit)

￿Socket power management register (CardBus socket registers offset 20h: 32-bit)

1.4.2System Sleeping State Consideration

Supporting sleeping states, such as SUSPEND, STANDBY, and HIBERNATION are important for a notebook PC environment. The following describes the sleeping state in APM systems:

1)SUSPEND

Reset signals G_RST and PRST are gated while SUSPEND is asserted. Power consumption of the PCI445X device is low if SUSPEND is asserted.

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Contents Implementation Guide Important Notice Read This First About This ManualCsr ±a /user/ti/simuboard/utilities Related Documentation From Texas Instruments Page Contents Viii Figures Tables PCI445X Device Topic±1. Typical System Architecture System Features Selection PCI and ISA Style Interrupt Socket Power SwitchesOptional PCI Signals Distributed DMA DdmaMiscellaneous Functions Description Socket Activity LEDsMFUNC7±MFUNC0 Terminal Assignments Serialized Interrupt ControlAsynchronous CSC Interrupt Generation CardBus Reserved Terminal SignalingPower Savings Mode Memory Burst R/W Operation Control12.11VCC Protection Socket Power Lock12.9 SMI ZV Port Control and Auto Detect FunctionPCI Bus Interface System ImplementationClamping Rails PERR, SERR, and LockPrst PCI reset and Grst Global reset INTA, INTB, and IntcPC Card Interface 4 2-Wire I2C Interface for EepromSocket power supply Damping resistor on Cclk terminal±1. Registers and Bits Loadable Through Serial Eeprom EepromSample PCI445X Eeprom Data File System Implementation 1 P2C Interface for TPS22X6 Power Switch Zoomed Video ZV InterfaceInterrupt Signaling Interface Miscellaneous SignalsRequirement of Pullup/Pulldown Resistors ±2. PC Card Interface Pullup Resistor List² ³±3. PCI Bus Interface Pullup Resistor List ±4. Miscellaneous Terminals Pullup Resistor List±5. Required Pullup/Pulldown Resistors LPSBios Considerations InitializationPCI Standard Registers Initialization System Sleeping State Consideration PCI TI Proprietary Registers InitializationRegister save/restore Docking System ConsiderationImportant Information Global Reset Only Bits, PME Context Bits TopicGlobal Reset Only Bits/PME Context Bits Table A±1.Global Reset Only Cleared BitsTable A±2.PME Context Bits Page PME and RI Behavior Table B±1.CardBus Ctschg and Wake-Up Signals Truth Table PME and RI BehaviorPCI445X Buffer Types Signal Name Terminal Type PCI445X Buffer TypesACVS2 BCAD22 GND PHYDATA6 ZVUV4 TSO Table C±2. Buffer Type Abbreviations Buffer Type Description
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