Texas Instruments PCI445X manual System Implementation, Clamping Rails, PCI Bus Interface

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System Implementation

1.2 System Implementation

This section describes signal connection for each interface, PCI bus, PC card interface, I2C interface, P2C interface, ZV interface, interrupt interface (parallel and serial), miscellaneous signals, and the PHY-Link interface. It also explains pullup/pulldown resistor requirements.

1.2.1Clamping Rails

The PCI445X device has three clamping rails: VCCA, VCCB, and VCCP. VCCA and VCCB are not power supplies for PC cards. After a card is powered up, the supply voltage to the card is fed back into the VCCA (or VCCB) input to the controller. This provides the controller a clamping level for signals to the card.

Technically the power switch controlling VCCA is also supplying power to the card via this signal, but actually VCCA is not a signal via which the controller supplies power to the card.

The PCI445X device only drives out a maximum signal of 3.3 V due to the 3.3-V core. This is not a problem, as 3.3 V is still seen as a logic 1 to a 5-V system.

￿VCCA and VCCB

PC Card interface clamping rails. CD1, CD2, VS1, VS2, and STSCHG/RI are not clamped, because these terminals should be able to signal without VCCA/VCCB.

￿VCCP

PCI bus interface clamping rail. It includes the MFUNC7/LOCK, MFUNC7±MFUNC0, IRQSER, GRST, and P2C terminals. It excludes INTA, INTB, INTC, and PME.

Note:

The PME/RI_OUT terminal uses an open drain (OD) buffer.

1.2.2PCI Bus Interface

￿PCLK, AD31±AD0, C/BE3±C/BE0, PAR, DEVSEL, FRAME, STOP,

TRDY, IRDY, GNT, REQ

These terminals can be connected to the system PCI bus directly. GNT and REQ are dedicated signals from the PCI bus arbitrator.

￿PERR, SERR, and LOCK

PERR and SERR are required signals. LOCK is an optional signal and available in MFUNC1, MFUNC3, and MFUNC7.

￿IDSEL

If there is a pulldown on LATCH, then the IDSEL will be routed to AD23, but the consequence of this is that the system designer must use AD23 as

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Contents Implementation Guide Important Notice Read This First About This ManualCsr ±a /user/ti/simuboard/utilities Related Documentation From Texas Instruments Page Contents Viii Figures Tables PCI445X Device Topic±1. Typical System Architecture System Features Selection PCI and ISA Style Interrupt Socket Power SwitchesOptional PCI Signals Distributed DMA DdmaMiscellaneous Functions Description Socket Activity LEDsMFUNC7±MFUNC0 Terminal Assignments Serialized Interrupt ControlAsynchronous CSC Interrupt Generation CardBus Reserved Terminal SignalingPower Savings Mode Memory Burst R/W Operation Control12.11VCC Protection Socket Power Lock12.9 SMI ZV Port Control and Auto Detect FunctionPCI Bus Interface System ImplementationClamping Rails PERR, SERR, and LockPrst PCI reset and Grst Global reset INTA, INTB, and IntcPC Card Interface 4 2-Wire I2C Interface for EepromSocket power supply Damping resistor on Cclk terminal±1. Registers and Bits Loadable Through Serial Eeprom EepromSample PCI445X Eeprom Data File System Implementation 1 P2C Interface for TPS22X6 Power Switch Zoomed Video ZV InterfaceInterrupt Signaling Interface Miscellaneous SignalsRequirement of Pullup/Pulldown Resistors ±2. PC Card Interface Pullup Resistor List² ³±3. PCI Bus Interface Pullup Resistor List ±4. Miscellaneous Terminals Pullup Resistor List±5. Required Pullup/Pulldown Resistors LPSBios Considerations InitializationPCI Standard Registers Initialization System Sleeping State Consideration PCI TI Proprietary Registers InitializationRegister save/restore Docking System ConsiderationImportant Information Global Reset Only Bits, PME Context Bits TopicGlobal Reset Only Bits/PME Context Bits Table A±1.Global Reset Only Cleared BitsTable A±2.PME Context Bits Page PME and RI Behavior Table B±1.CardBus Ctschg and Wake-Up Signals Truth Table PME and RI BehaviorPCI445X Buffer Types Signal Name Terminal Type PCI445X Buffer TypesACVS2 BCAD22 GND PHYDATA6 ZVUV4 TSO Table C±2. Buffer Type Abbreviations Buffer Type Description
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