Texas Instruments TMS320C6712D warranty Cache configuration Ccfg register description, L2MODE

Page 42

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

cache configuration (CCFG) register description

The device includes an enhancement to the cache configuration (CCFG) register. A “P” bit (CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2 memory.

For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory accesses blocked, see the TMS320C6712, TMS320C6712C, TMS320C6712D Digital Signal Processors Silicon Errata (literature number SPRZ182C or later).

31

30

10

9

8

7

3

2

0

 

 

 

 

 

 

 

 

 

P†

Reserved

 

IP

ID

Reserved

 

 

L2MODE

R/W-0

R-x

 

W-0

W-0

R-0 0000

 

 

R/W-000

 

 

 

 

 

 

 

 

 

Legend: R = Readable; R/W = Readable/Writeable; -n= value after reset; -x = undefined value after reset

†This device includes a P bit.

Figure 7. Cache Configuration Register (CCFG)

 

 

 

 

Table 18. CCFG Register Bit Field Description

 

 

 

 

 

 

BIT #

NAME

 

 

 

DESCRIPTION

 

 

 

 

 

L1D requestor priority to L2 bit.

31

P

P

=

0: L1D requests to L2 higher priority than TC requests

 

 

P

=

1: TC requests to L2 higher priority than L1D requests

 

 

 

30:10

Reserved

Reserved. Read-only, writes have no effect.

 

 

 

 

 

 

Invalidate L1P bit.

 

9

IP

0

=

Normal L1P operation

 

 

 

1

=

All L1P lines are invalidated

 

 

 

 

 

 

Invalidate L1D bit.

 

8

ID

0

=

Normal L1D operation

 

 

 

1

=

All L1D lines are invalidated

 

 

 

7:3

Reserved

Reserved. Read-only, writes have no effect.

 

 

 

 

 

L2 operation mode bits (L2MODE).

 

 

000b

= L2 Cache disabled (All SRAM mode) [64K SRAM]

2:0

L2MODE

001b

= 1-way Cache (16K

L2 Cache) / [48K SRAM]

010b

= 2-way Cache (32K

L2 Cache) / [32K SRAM]

 

 

 

 

011b

= 3-way Cache (48K

L2 Cache) / [16K SRAM]

 

 

111b

= 4-way Cache (64K

L2 Cache) / [no SRAM]

 

 

All others Reserved

 

 

 

 

 

 

 

42

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Contents SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA package bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PackageBottom View Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6712D Processor C6712DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description DA2 ST1DA1 ST2Memory map summary Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register NameEdma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersJtag Signal groups descriptionClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst BIG/LITTLE EndianCLKS1† TOUT1 TINP1CLKR1 GpioDevice Configurations Device configurations at device resetEmifbe Configuration GDP/ZDP Functional Description PINBOOTMODE10 LendianDevcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP EMU1B9 EMU0D9 IPU BootmodeBOOTMODE1 C19 BOOTMODE0 C20 IPD LITTLE/BIG Endian FormatEdge-driven IPD Description Name GDP IPU‡ ZDP Resets and InterruptsOnly one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − Address # Emif − Data #IPD Description Name GDP IPU‡ ZDP Emif − Data # TIMER1TIMER0 Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleReserved for Test RSV IPD IPD Description Name GDP IPU ZDPRSV IPU Additional Reserved for TestSPRS293A − October 2005 − Revised November Dvdd Name GDP ZDP Supply Voltage PinsSee the power-supply decoupling portion of this data sheet CvddVSS Description Name GDP ZDP Supply Voltage PinsGround Pins GNDSignal Name PIN GDP ZDP TYPE† VSS GNDDescription GDP Name ZDP Ground Pins VSSDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Device Family Temperature Range Default 0C to 90CPrefix TechnologyDocumentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIECPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector EventEdma module and Edma selector Edma ChannelsEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX UnitClock Signal PLL Clock Frequency Ranges†‡GDP 150and ZDP Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply design considerations Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerationsGND Dvdd Power-supply decouplingSupply Schottky Diode Core Supply C6000Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedReset Emif big endian mode correctnessBootmode Emif Data Lines Pins Where Data PresentRecommended operating conditions MIN NOM MAX UnitIOH Parameter Test Conditions MIN TYP MAX Unit IOZ42 Ω Signal transition levelsParameter Measurement Information Vref = 1.5AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Input and Output Clocks Timing requirements for CLKIN†‡§See Figure Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3MIN Eclkin EclkoutSee −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡ AreED150 Read Data Setup = Strobe = Not Ready Hold =CE30 BE10 EA212 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyCEx BE30 EA212 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAXEA212 ED150 CE30 BE10BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure150 Read Eclkout EA2113 Bank EA112 Column EA12 ED150AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 ED150 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Dcab EclkoutEA112 EA12 ED150 Deac EclkoutCE30 BE10 EA2113 Refr EclkoutMRS Eclkout CE30 BE10 EA212 MRS value ED150Hold HOLD/HOLDA TimingTiming requirements for the HOLD/HOLDA cycles† see Figure Hold HoldaBusreq Timing Eclkout BusreqReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Emif Z Group † Emif Low Group † Boot and DeviceExternal Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see FigureParameter Bitn-1 Clks ClkrFSR int ClkxFSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave Unit MIN MAXParameter MASTER§ Slave Unit MIN MAX Clkx FSXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Jtag TEST-PORT Timing Timing requirements for Jtag test port see FigureUnit MIN MAX TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical DataMSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
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